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Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs

Chapter 2 SiC MOSFET Reliability Characterization

Within this chapter an overview of techniques to extract device parameters, e.g. the threshold voltage Vth and flat-band voltage Vfb, based on electrical characterization methods is presented. Furthermore, widely employed measurement schemes to extract the device parameter degradation, namely the drift of the threshold voltage ∆Vth over time and gate leakage currents (math image), are introduced. Additionally, the custom-built measurement tools used to extract the data presented in this work are discussed and the advantages and drawbacks of the setups outlined. Finally, the peculiarities of the presented methods when applied for reliability characterization of SiC MOSFETs are highlighted, based on the findings presented in [134, 90, CSJ10].

2.1 Electrical Characterization Methods

An important device parameter that can be altered during device operation is the threshold voltage Vth. It is loosely defined as the bias state at which a significant conducting channel is formed at the MOS interface. Another important MOSFET parameter is the subthreshold-slope \( SS = \partial V_\mathrm {G} / \partial \mathrm {log}\left (I_\mathrm {D}\right ) \) as it is decisive for defined switching between ON and OFF state within a small gate bias range. Additionally, the trans-conductance \( g_\mathrm {m} = \partial I_\mathrm {D} / \partial V_\mathrm {G} \) is mostly related to the carrier mobility which is correlated to scattering at interface defects [135]. In practice, electrical characterization methods are used to extract these parameters as well as to track aging of these parameters during stress experiments. An overview of the most important extraction methods for MOSFETs is given in this section, with focus on Vth extraction and its variation over time due to bias and temperature stress, the two most dominant parameters for BTI.

2.1.1 Transfer Characteristics


Figure 2.1: The extraction of Vth (left) is shown with a constant current of ID = 1 µA (blue), the linear extrapolation (red) and the second derivative method (magenta) for a lateral SiC-MOSFET test structure with W \( \times \) L = 100 \( \times \) 8 µm2 and VD = 0.1 V at elevated \( T \) = 550 K (c.f. Figure 1.4). Additionally, the computed trans-conductance \( g_\mathrm {m} \) with its maximum value marked and the second derivative of the logarithmic drain current with the required minimum are also shown (right).

The transfer-characteristics is defined as the relation of the drain current ID over the gate bias VG recorded at a constant drain bias VD and can be used to extract the current state of device parameters at the time of measurement. It is typically recommended to sweep the gate bias VG of the Device Under Test (DUT) and measure ID at each bias point as fast as possible. This aims to minimize the duration of an applied oxide stress field during the sweep to suppress the impact of defects with shorter capture and emission time constants compared to the sweep duration as much as possible. As a consequence, fast sweeps conserve the pristine device state. As the theoretical definition of Vth, the exact equilibrium of majority and minority carriers in the conducting channel of a MOSFET [31], cannot be experimentally accessed, other definitions of Vth are required for its experimental extraction [136]. Most frequently, Vth is accessed via the transfer characteristics of the MOSFET by applying a constant source-drain current criterion

(2.1) \{begin}{align} V_\mathrm {th \vert I_{D,const}} = V_{\mathrm {G} \vert I_\mathrm {D} = \mathrm {const}}. \{end}{align}

The current ID is thereby typically chosen to be scaled by the device geometry with

(2.2) \{begin}{align} I_\mathrm {D} = I_\mathrm {ref} \frac {W}{L} \{end}{align}

at a constant VD when comparing MOSFETs with different channel geometries. \( I_\mathrm {ref.} \) is typically chosen to result in a drain current within the sub-threshold region of the transfer characteristics. The ease of application of the method and a low extraction variability, when used for wafer scale device (math image) variations, make the constant current method suitable for the extraction of ∆Vth over time [137].

Alternative methods use the trans-conductance

(2.3) \{begin}{align} g_\mathrm {m} = \frac {\partial I_\mathrm {D}}{\partial V_\mathrm {G}} \{end}{align}

to determine Vth from the ID (VG ) characteristics. For example, the linear extrapolation method uses the gate voltage for the maximum transconductance \( g_\mathrm {m,max} \) to extrapolate to zero drain current. By subtracting VD / 2 from the resulting intersection gate bias, Vth is obtained as [138]

(2.4) \{begin}{align} V_\mathrm {th,g_{m,lin}} = \frac {I_{\mathrm {D\vert }g_\mathrm {m,max}}}{g_\mathrm {m,max}} - V_{\mathrm {G\vert } g_\mathrm {m,max}} - \frac {V_\mathrm
{D}}{2}. \{end}{align}

The second derivative method allows for a better comparison with the theoretical value of Vth by defining the gate bias at the minimum of the second derivative of the logarithmic drain current as threshold voltage [139]. Figure 2.1 shows a comparison of the extraction methods for a lateral SiC-MOSFET with a simple architecture, i.e. no JFET or drift-region are present contrary to a DMOS or trench design. Hence, these test structures allow for solely characterizing the channel degradation. A large variation of ∆Vth = 3.55 V between the presented extraction methods on this technology emphasizes the importance of using a unique definition of the (math image) extraction method when comparing absolute (math image) values, especially in SiC technologies.

The parameter extraction methods described above have been established for mature Si technologies and it is implicitly assumed that during the bias sweep the transistor parameters do not change. However, this assumption does not generally hold true for other material systems, such as two-dimensional channel based transistors [140] and SiC/SiO2 MOS structures [141]. Both systems show a distinct transfer-characteristic hysteresis, as a result of charge that is captured during the bias up-sweep and not emitted during the down-sweep. This asymmetry of the capture and emission processes leads to a shift of the transfer characteristics to more positive voltages during the subsequent down-sweep (in the case of a nMOS), as shown in Figure 2.2. The peculiar shape of the hysteresis depends on the device temperature, as well as the voltage sweep rate and start and end bias of the sweep [CSC7, CSJ4].


Figure 2.2: Transfer characteristic hysteresis is shown for a narrow gate bias up- and down-sweep of lateral SiC/SiO2 MOSFET test structures. A distinct hysteresis can be measured at room temperature, depending on the voltage sweep-rate, while at higher temperatures the effect becomes less pronounced (originally published in [CSC8]).

2.1.2 Capacitance Voltage Measurements

The measurement of the small-signal capacitance of a MOS stack is a widespread technique to obtain unknown information about the transistor gate stack, i.e. oxide thickness, doping densities, poly-Si gate-depletion and permittivity. Additionally, variation of the measurement parameters and comparison of the resulting changes in shape of the Capacitance-Voltage (CV) curves allows for extraction of defect properties. For CV measurements, a DC voltage is applied at the gate contact and superimposed with a sinusoidal AC signal with a small amplitude. The bulk contact of a MOSCAP (or all terminals - source, drain and bulk - in case of a MOSFET) remains grounded. Initially, the DC bias is swept typically from the accumulation to the strong inversion regimes. At each DC step the gate current is recorded over a number of AC periods and the measured gate current signal is modulated by the applied gate voltage signal to compute the impedance of the MOS stack from the phase shift and signal amplitudes. Furthermore, in subsequent measurements, the frequency of the applied AC signal is often varied from the kHz to MHz regime. Thus, depending on the charge transfer kinetics of defects in the oxide and/or at the interface, the shape of the CV curve may change. When a high number of defects, which exhibit charge capture and emission times in the range of the gate sweep duration, is present also a distinct hysteresis in the CV characteristics may be observed, as is the case in SiC MOSFETs. As shown in Figure 2.3, the CV measurement is considerably influenced by defects at low frequencies and significantly deviates from the ideal (defect free) case.


Figure 2.3: Capacitance (left) and conductance (right) of a lateral SiC MOSFET measured in gated diode configuration [142, 143] at low frequencies of f = 2 kHz, 4 kHz, 8 kHz and 16 kHz are shown for sweeps from accumulation to strong inversion (blue - solid) subsequently and vice versa (blue - dashed). Compared to the ideal (defect free) curve (green) calculated by solving the Poisson equation numerically for the gate stack, the impact of fixed charge and dynamic charge exchange becomes clearly visible. The whole characteristics is shifted towards negative biases (fixed positive charge) and the reduced steepness of the accumulation and inversion branches is likely a result of the large number of interface defects.

In Si MOS devices, the quasi static CV measurement allows for the extraction of the surface potential over the gate bias ψs(VG), c.f. (4.57) and (4.58). This method is not straight-forward to apply in SiC MOS devices due to the large deviation from the ideal CV characteristic, as is compared for in Figure 2.3. Thus, in order to reproduce the measurement, a transient self-consistent computation of the Poisson equation, taking the occupation of the defects into account, is required to obtain the SiC MOS CV shape. Note that such self-consistent simulations are computationally expensive and are thus often omitted.

Based on CV measurements, a number of methods to extract interface state densities have been developed, e.g. Terman-, Conductance- or the High-Low method. However, these methods have been established based on observations in Si-based MOSFETs and are based on assumptions such as for example that defects may only be charged and discharged below a certain AC signal frequency. Additionally, these assumptions often rely on the prerequisite that the defects simply follow Shockley-Read-Hall like transition kinetics. Thus, these methods are not directly applicable to SiC MOSFETs and have to be adapted if considered for application with SiC MOSFET [22].

2.1.3 Measure-Stress-Measure Schemes

As indicated by the name, the Measure Stress Measure (MSM) schemes consist of three phases. After an initial minimally-intrusive measurement of the pristine device state (typically with a (math image)( (math image)) curve recorded within a small bias range), the DUT is stressed at elevated electric fields, temperature or irradiation compared to regular device operation conditions. This stress phase aims to accelerate device parameter degradation compared to regular operation, in order to be able to obtain the degradation within a reasonable experimental time. Following the stress phase, the device state is measured again and the quantities of interest are compared with their initial state. A regular MSM sequence typically consists of multiple stress and measure phases that are applied subsequently. In the extended MSM (eMSM) scheme [144], the recovery of the device parameters, i.e. (math image), mobility or channel conductivity in case of continuous (math image) measurement, is monitored over a period of time during the measurement phase. Furthermore, the schemes can vary in terms of the duration and amplitude of the bias stress applied. For instance, in the constant voltage stress (CVS) scheme the stress duration (and alternatively also the measurement duration) is extended within each subsequent stress phase maintaining a constant stress bias.


Figure 2.4: Different bias stress MSM schemes used throughout this work are shown. The CVS eMSM sequence (bottom) consists of stress phases of constant gate bias with subsequently increased duration. Conversely, in the RVS scheme (bottom, center) the stress time is kept constant while the stress bias is increased after each recovery phase. A pulsed MSM sequence (top, center) allows to (partly) separate fast from more permanent degradation in SiC technologies. The AC stress scheme (top) is used to study Vth shifts during operation relevant AC conditions, by interrupting the AC signal at different intervals in the AC duty cycle. (partly taken from  [CSJ6])

Conversely, in the ramped voltage stress (RVS) scheme [145], the stress duration is kept constant, while the bias is increased at each stress phase. In order to investigate the degradation at operation relevant AC conditions, a variation of the CVS-MSM scheme replacing the constant DC stress by a digital AC stress signal was proposed and demonstrated in [83]. The scheme allows to investigate the short time Vth variation by interrupting the AC signal at different points during an AC duty cycle. A combination of both, CVS and RVS schemes, has also been suggested and termed accelerated capture emission (ACE) measurement pattern [146]. Within this scheme, the stress voltage and periods are increased subsequently, and also the read-out bias is varied from inversion to accumulation regime during one readout phase. This results in an accelerated charge capture and emission within the experimental time window compared to individual CVS and RVS schemes. For further optimization of the efficiency of the experiment, a variation of the eMSM scheme including temperature ramps to accelerate the device recovery has been proposed [89]. Figure 2.4 gives an schematic overview about the different MSM schemes used throughout this work. The major drawbacks of the MSM methods are the lack of information about device degradation during the stress phase, as well as the inherent measurement delay when switching from stress to recovery bias. Even with ultra-fast measurement setups [147] this delay exceeds 1 µs. As a consequence, depending on the technology investigated, a major part of the faster device recovery remains inaccessible.

To overcome this drawback and to investigate degradation during the stress phase the On-The-Fly (OTF) method, also known as three-point or non-relaxation characterization method  [148, 149], has been proposed. The channel conductance is obtained by recording the drain current, while pulsing the gate bias with small variations around the stress voltage level (typically at three points), with a small drain bias applied. This allows to record the change of the operation point of the transfer characteristics with minimum interruption of the stress phase. However, as only selected points of the ID (VG ) can be measured, the interpretation of the results becomes challenging and capture events with smaller transition times due to the inevitable gate bias switching delay, are not accessible by this technique. OTF extractions of ∆Vth during bias stress have been conducted for PBTI [150] and NBTI [151] in SiC MOSFETs revealing significantly larger (math image) shifts compared to MSM studies.

2.1.4 Single Charge Transfer Measurements

The characterization methods (MSM, OTF) presented above are mainly employed to characterize continuous degradation and recovery of large area MOSFETs. These devices typically show a continuous recovery signal of the channel conductivity after being subjected to bias and temperature stress. The change in device behavior is a result of the superposition of many single charge emission events from a large ensemble of defects that has been charged within the stress phase. With ongoing down-scaling of the device geometry to a few nm technology nodes, the number of electrically active defects has reduced to a few single traps within the vicinity of the channel area in modern CMOS transistors. At the same time the impact of a single defect on the channel conductivity has increased with the reduced active channel area [152]. These circumstances (reduced number of defects and decreased conductivity upon charging) allow to study single charge capture and emission events in small area transistors. By extracting the statistically distributed properties of these events, e.g. charge capture and emission time constants, many details about the charge transfer kinetics can be revealed. Commonly, two measurement techniques are employed for the extraction of the charge capture and emission events. Both methods are based on measuring fluctuations of the channel conductivity, i.e measuring the drain-source current at a constant drain and gate bias.

In the TDDS method [71], the statistical distribution of the single charge emission events is analyzed based on a large number \( N \) of repeated gate bias stress and measure sequences, typically \( N \) \( \approx \) 100 is used. Within this method, each defect can be identified by its step height \( \eta \), which is dependent on the defects lateral and perpendicular position relative to the current percolation path. In contrast to the charge emission times, the capture times are not directly accessible, but can be derived from the average defect occupancy for the applied stress time, which is changed subsequently. The method is applicable for defects with asymmetric capture and emission times at the applied bias and temperature conditions. Due to the large number of repetitions required to extract statistical properties, the time window for the recovery trace extraction has to be limited to about \( t_\mathrm {recovery} < \) 1 ks to yield reasonable experimental times [153]. The TDDS applied to a Si based MOS technology has revealed two different types of defects, termed fixed and switching emission time constant traps [71, 75]. The explanation of the latter requires an additional meta-stable defect state, which has been one of the main requirements for the development of the four-state defect model [70, 73].

(image) (image)

Figure 2.5: First 10 s of an RTN signal are shown as extracted on a nMOSFET at \( T \) = 9 K (left). The electron capture (green) and emission (blue) times \( \tau _\mathrm {c/e} \) and events \( \eta _\mathrm {c/e} \) are highlighted. The transition times are exponentially distributed as shown in the histograms and Gaussian fits (lines) (right). (originally published in  [CSC4


Figure 2.6: A comparison between the scaling requirements for single defect analysis in Si/SiO2 and SiC/SiO2 MOS gate stacks is shown. The interface state densities for calculating the number of defects for a given active channel area were chosen as \( N_\mathrm {it,Si} = \SI {5e9}{\per \electronvolt \per \square \centi \meter } \) and \( N_\mathrm {it,4H-SiC} = \SI {5e11}{\per \electronvolt \per \square \centi \meter } \) inline with values reported in literature. SiC MOSFETs produced for harsh environment CMOS applications reported in literature [154, 155, 156] (triangular symbols) with the smallest available chan- nel areas contain still numbers of defects which are magnitudes above those required for single defect detection.

Measuring RTN signals in small area devices allows to study defects with similar capture and emission time constants τc \( \approx \) τe within a single measurement trace. This is typcially the case when the Fermi-level of the channel is aligned to the thermodynamic trap level ET of the defect. Figure 2.5 shows an exemplary RTN signal and analysis of a Si-based MOSFET conducted at cryogenic temperatures. This study revealed that RTN in the CMOS devices used in quantum computing control circuits does not freeze out, contrary to defects responsible for BTI. It has to be noted, that as is the case for TDDS signal evaluation, a large Signal-to-Noise Ratio (SNR) is required to reliably detect the individual steps of a RTN signal.

Defect analysis by the RTN technique has been used to obtain charge transfer kinetics of defects in various MOS material systems, including standard Si-based [134], two-dimensional channel [157] and also wide bandgap substrate materials as GaN [158]. However, to date, no such studies have been conducted in a SiC/SiO2 MOSFET. There are no obvious limitations that would obstruct the technique from its application, however, no devices with channel areas small enough to reveal single defect charge transfer events have been fabricated so far. The main reason for this is that SiC devices are mainly intended for power electronic applications where there is no requirement for scaled devices. An approximation of the minimum channel scaling required for RTN analysis in SiC MOSFETs is given in Figure 2.6, together with experimental small area SiC transistors reported in literature. The extrapolation of the device area together with a typical SiC MOSFET interface defect density shows that scaling of these structures by about another four orders of magnitude could allow for SiC/SiO2 channel single defect studies.

The noise spectra of individual RTN signals of single defects that are superimposed in large area devices manifests itself in a 1/f like behavior [67]. Such spectra have been measured and analysed in SiC MOSFETs [159, 160]. The authors suggest that the origin of the low-frequency noise is solely interface defect related by comparing the data with charge-transition levels used in TCAD and compared to such obtained by ab-inito calculations.