Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs
To the best of the author´s knowledge, modeling efforts related to charge-trapping in SiC MOSFETs have either been limited to empirical approaches, describing the time dependent degradation by a power-law, or to the extraction of capture and emission activation energy maps from measurement data. Going significantly beyond these efforts, BTI modeling presented here is based on device level simulations, relying solely on physical material parameters to parameterize two-state NMP transitions in large ensembles of pre-existing oxide and interfacial defects. Based on a novel effective single defect extraction algorithm, large experimental data sets have been used to extract defect parameters in different DMOS technologies, which are comparable in their electron trap distributions, but significantly differ in their hole trap distributions and thus NBTI characteristics. Due to the large variety of defects that can potentially form in SiC/SiO2 MOSFETs and the wide active energy range allowing for defects almost in the entire SiO2 bandgap to get charged and discharged, no single candidate can be identified to explain the defect distributions common among the technologies.
A novel approach for modeling TAT currents based on a deterministic solution of the hopping Master equation has been proposed and parameterized to explain leakage currents in SiC/SiO2 structures in detail for the first time. Additionally, the model has been validated by reproducing well explored leakage characteristics in TZT capacitors. The parameters determining the charge transfer kinetics allow for a comparison to ab-initio calculations, rendering polarons likely defect structures to enable TAT currents in material systems employing amorphous binary oxides as dielectric layers.