Modeling of Defect Related Reliability Phenomena
in SiC Power-MOSFETs

Chapter 5 Measurements, Simulations and Results

BTI and gate-leakage currents are considered major reliability threats responsible for device parameter degradation in SiC MOSFETs. Their characterization and simulation by accurate models are presented within this section. The Si-face interface of SiC to its deposited or grown native oxide has been intensively studied in the past. Thus, investigations of charge trapping by inelastic tunneling processes as presented here, mainly focusing on lateral MOS test structures and commercially available DMOS devices.

First, BTI is analyzed on lateral MOSFET test-structures by employing a bias pulse technique to separate fast and slow degradation components for both pBTI and nBTI degradation. Based on these findings different DMOS technologies are characterized by a large measurement data set and, using the newly developed ESiD algorithm, therefrom defect parameters are extracted which reveal similarities, but also differences among the defect bands in the SiC MOSFETs.

In the second section, gate leakage currents are analyzed based on enhanced temperature activated TAT currents observed at low to medium field strengths employing a SiC/SiO₂ MOSCAP, a MOSFET, and a MIM capacitor with ZrO₂, as used in RAM applications. The newly proposed TAT model is demonstrated and reveals details about the charge trapping kinetics within these structures and by a comparison of the defect parameters with ab-initio computations, a class of defects is identified as TAT transition centers in both binary oxides.

5.1 Bias Temperature Instabilities in SiC MOSFETs

The results within this section have been previously published in [CSC8],[CSJ6] and [CSC1].

This section aims to reveal the underlying physical mechanisms that cause the main features of BTI as observed in SiC MOSFETs, which are frequently compared to BTI in Si technologies [88, CSC5, 90] by applying the same characterization and data analysis methods. For this purpose, defect parameters are extracted by device scale simulations and restricted to be consistent within bounds defined by ab-initio calculations of likely defect candidates. Similarities and differences among different SiC DMOSFET technologies and Si based MOSFETs in terms of the origin of BTI are also discussed.

5.1.1 Lateral Test Structures

Some of the advantages of studying the impact of charge trapping as the main reason for (math image) and R_on shifts on lateral structures include:

• A uniform electric field distribution across the oxide can be assumed for small enough drain bias.
• Geometrical effects, e.g. edge effects due to trench sidewalls, can be neglected.
• A small contact resistance is assumed and an additional series resistance as in vertical device architectures is not expected to influence on the ∆V_th extraction.
• The band offsets and other material parameters, e.g. transition region width between SiC and SiO₂, are best studied for the Si-face SiC/SiO₂ interface, compared to a-face, c-face or m-face surface planes.

Hence, planar SiC/SiO₂ MOSFETs with channel dimensions of W $\times$ L = 100 $\times$ 2 µm², 4 µm² and 6 µm² and an oxide layer with a thickness of about 70 nm have been investigated. After the oxide deposition, the devices have received an annealing process step in NO ambient.

An initial (math image) ( ) curve to convert the measured drain current into ∆V_th is recorded as shown in Figure 2.2 on a pristine device for each BTI stress sequence. To determine the threshold voltage shift with a reduced perturbation of the ( )-curve due to charge trapping during the gate bias sweep, these time-zero transfer characteristics are measured at a rate of $R$ = 50 V/s and within a narrow bias range of only up to about 1 V above the threshold voltage. The selected sweep rate is the fastest for the chosen current limit of $I_\mathrm {max} = \SI {1}{\micro \ampere }$ for the ultra-low noise Defect Probing Instrument (DPI) used for this characterization. A constant current criterion of I_D = 100 nA is used to convert I_D to ∆V_th and the drain bias has been scaled with L by V_D = 0.1 V, 0.2 V and 0.3 V. Without any additional delay after recording the pristine (math image) ( ) characteristics, an eMSM scheme is applied with stress times ranging from tstr = 1 × 10⁻⁶ s to 1 × 10⁴ s and recovery times trec = 10 s to 1 × 10⁵ s with the first measurement point extracted after $t^\mathrm {delay}$ = 100 µs. For the PBTI characterization, the stress bias has been selected as $V_\mathrm {G}^\mathrm {s}$ = 30 V, 37.5 V and 45 V, resulting in approximate oxide stress fields of $E_\mathrm {ox}^\mathrm {str} \approx$ 3.5 MV/cm, 4.6 MV/cm and 5.7 MV/cm. The recovery bias $V_\mathrm {G}^\mathrm {r}$ is chosen according to the extracted $V_\mathrm {th,0} \approx$ 4.4 V. All measurements have been conducted on the custom-built low-noise DPI presented in Section 2.3 and each eMSM scheme is recorded on a fresh n-MOSFET.

The material parameters that were used to calculate the electrostatic quantities in Comphy (c.f. Section 4.6.1) are listed in Table 5.1 for the channel substrate and in Table 5.2 for the insulating layer. The transition of the band edges between the channel and the oxide is assumed to be abrupt and the band edges are thus linearly interpolated for the simulation within the first 5 Å as shown in the band diagrams in Figure 5.1.

For the extraction of the defect parameters, defects are considered uniformly distributed on an equidistant spatial grid $x_\mathrm {T}$ and normally distributed on a equidistant energetic grid ( $E_\mathrm {R}$ , $E_\mathrm {T}$ ). Each grid point ( $x_\mathrm {T}$ , $E_\mathrm {R}$ , $E_\mathrm {T}$ ) is weighed by this distribution to yield the selected total defect density $N_\mathrm {T}$ , with the grid parameters given in Table 5.3.

Using these settings, the defect parameters of two bands are extracted by minimizing the difference between the simulation results and the measurement data by a Nelder-Mead least-square minimization algorithm [245] as implemented in scipy. As initial guess, a shallow defect band extracted on Si/SiO₂ technology [235] has been used and with ET close to $E_\mathrm {c,SiC}$ that is sampled up to 3 nm into the oxide. A good agreement with the measurement data for the tails of the recovery traces is revealed in Figure 5.1 (top). For the calculation of the remaining fast recovering ∆V_th defects with small relaxation energies and located within the transition region at a distance of up to 5 Å from the interface have been introduced, resulting in a fast electron trap band (EB). These defects define the charge transfer kinetics as required to explain the fast recovering component of ∆V_th and lead to degradation of ∆V_th $>$ 2 V for the longest stress phases. Note that the small $E_\mathrm {R}$ used in the fast EB effectively yield transition rates that can also be approximated by employing the extended-SRH model, as discussed in Chapter 4 and in detail by Ruch et. al [208].

$ \overline {E}\sub {T} \pm \sigma _{E_\text {T}} $

To investigate the impact of bias switches to the depletion and accumulation regime, as for instance proposed in [87] for an evaluation of V_th shifts in parallel for many devices, pulsed MSM sequences have also been measured and included in the fitting routine, as shown in Figure 5.2. Thereby, a pulse at a bias level in the depletion ( $V_\mathrm {G}^\mathrm {p}$ = 0 V) or accumulation ( $V_\mathrm {G}^\mathrm {p}$ = −5 V) regime is applied after the stress phase before the recovery phase is started for $t^\mathrm {p}$ = 10 s. Initially, only the pulse is applied without stress to investigate the impact of the pulse on the pristine device.

When splitting the contributions of the defect bands in the simulation, it is revealed that the shallow EB solely accounts for the characteristic recovery traces for a pulse bias of $V_\mathrm {G}^\mathrm {p}$ = 0 V, shown in Figure 5.2 (top). Note the degradation of ∆V_th at the beginning of the recovery traces. This increasing ∆V_th at recovery conditions is a result of electron capture of a small fraction of defects in the shallow EB, that previously emitted charge during the pulse phase. Quite to the contrary, all defects in the fast band emit the previously captured electrons during the pulse duration. Furthermore, the application of an accumulation pulse results in a different recovery characteristic, starting at negative ∆V_th. This NBTI characteristics is a result of hole capture and can be accounted for by the introduction of two hole trap bands (HB1, HB2) with parameters listed in Table 5.4. These bands together with the two EBs are able to reproduce the peculiar ∆V_th recovery at all pulse conditions shown in Figure 5.2 (bottom).

Moreover, the NBTI bias dependence is extracted by measuring a RVS MSM scheme with an initial readout at the recovery bias and stress bias variation in the range of $V_\mathrm {G}^\mathrm {s}$ = −2.5 V to −25 V at fixed stress time of $t^\mathrm {s}$ = 1 ks and readout time of $t^\mathrm {r}$ = 10 ks, as shown in Figure 5.3 (left). It has to be noted that even if the extraction of NBTI in an nMOS is operation relevant when bipolar gate drivers are used, a large fraction of defects capturing holes at negative bias already have emitted their charge before the read-out phase. Hence, only a small fraction of defects contributing to NBTI is experimentally accessible with MSM sequences conducted in n-channel MOSFETs. Note that the NBTI results on experimental pMOS structures investigated in [251] show significantly larger (math image) shifts compared to those of the n-MOSFETs presented in this work.

The accurate reproduction of the temperature activation in the simulation is mainly influenced by the relaxation energy $E_\mathrm {R}$ within the NMP model as shown in Figure 5.3 (right) for both PBTI and NBTI MSM sequences. Again, in Figure 5.3, the impact of an initial readout phase at V_G $\approx$ V_th prior to the stress phase is shown by the black line. This readout shows that already the application of the readout bias leads to electron trapping and hence (math image) shifts of more than ∆V_th = 0.1 V for tread = 10 ks.

To further strengthen the hypothesis of the shallow EB band being an intrinsic property of the oxide, a PBTI MSM sequence has been measured on a commercially available trench MOSFET [252, 253]. The inset of Figure 5.4 shows the initial transfer characteristics used to extract (math image) with steeper $\mathit {SS}$ and lower compared to the lateral device. Thus, the device electrostatics in Comphy have been adapted for the reduced initial by changing the channel doping concentration to compensate for the difference. The first point of the recovery trace could not be resolved below 100 ms due to the large input capacitance of the trench device. As shown, the long-term recovery behavior is again captured well by the simulation and can solely be described by the shallow EB with the same parameters as given in Table 5.4. Increasing the defect density of the fast EB by about a factor of 1.5, finally leads to a reasonable agreement of the computed short term ∆V_th with the measurement. The increased density thereby compensates for the different interfacial properties obtained on Si-face when compared to a-face terminated SiC MOSFETs. It has to be emphasized that the comparatively large PBTI shifts in SiC MOSFETs does not contradict the fact that PBTI is almost negligible in Si/SiO₂ technologies, as the active defects are not accessible in the Si based devices due to the difference of about 0.3 eV in the conduction band offsets between Si/SiO₂ and SiC/SiO₂ [254]. A comparison of the PBTI degradation of different SiC technologies [CSC5] to Si-based MOSFETs is shown in Figure 5.5 together with a comparison of the AERs available in both systems. In order to acquire only the long-term BTI component for the SiC characterization, a preconditioning scheme employing negative pulses has been used to remove the fast degrading and recovering components. Thus, the long-term degradation shows a similar trend as in the Si technology with an increased absolute ∆V_th of up to a factor of 200.

5.1.2 Comparison of different DMOS Technologies

As large differences in (math image) shifts have been reported for different SiC MOSFETs [255, 88] for both negative and positive BTI, three different n-channel DMOSFETs from two vendors are analyzed in terms of their BTI recovery trends and defect distributions that explain each peculiar ∆V_th recovery characteristics. The differences may arise from various influences during device manufacturing such as POA under different nitrogen containing precursors (NO, NO $_\mathrm {2}$ , NH $_\mathrm {3}$ ) and annealing temperatures or channel counter-doping for increased mobility [52, 53] and off-axis epitaxial growth.

With the same argument as in Section 5.1.1 that the Si-face SiC/SiO₂ interface is best studied compared to other SiC surface terminations, three different DMOSFET devices are analyzed. Thereby two technologies are the second (T1/G2) [256] and third generation (T1/G3) [257] of the same vendor, and the third one is the first generation of a different vendor (T2/G1) [258]. In order to guarantee comparability, devices with similar oxide thicknesses were chosen, differing only in a few nanometers, so that the applied stress biases result in similar electric field strengths.

Contrary to the lateral test structures, the measurement setup used to extract (math image) shifts [147] consists of a feedback loop, in which an operational amplifier forces a constant drain current of I_D = 1 mA through the channel by regulating V_G at fixed V_D (c.f. Figure 2.7 (right)). Besides the direct readout of ∆V_th $(t)$ = $V_\mathrm {G}(t) - V_\mathrm {G}(0)$ , an additional advantage is that the first read-out can be conducted after only $t^\mathrm {delay} \approx$ 1 µs. Two types of MSM schemes are used to characterize the short and long-term ∆V_th shifts. For operation relevant short term shifts, an AC MSM scheme [83] is used (c.f. Figure 2.4 (top)), in which an AC stress signal is applied for tstr = 100 ms at a frequency of $f = \SI {50}{\kilo \hertz }$ at a constant high V_G^H and low bias V_G^L. This stress phase is interrupted at different points within the last AC signal period, and a recovery trace is recorded for 10 ms by forcing the constant threshold current through the channel as described above. This scheme is repeated for 20 different interruption points that are logarithmically distributed across the high and low phase of the last AC period of the stress phase. The total AC stress MSM sequence has then been permuted for different elevated operation voltages of V_G^H = 15 V and 20 V and V_G^L = −2 V, −5 V and −7 V. While this sequence covers all the short term drifts of (math image) expected during an AC signal period at regular operation, additionally DC CVS MSM sequences (c.f. Figure 2.4) with increased stress bias ( $V_\mathrm {G}^\mathrm {str} = \SI {25}{\volt }$ ) have been measured to capture the long-term degradation. In order to justify the extrapolation of ∆V_th beyond the experimental time window and to obtain the temperature activation of charge trapping, all sequences have been repeated at $T$ = 448 K.

For calculating ∆V_th, as described in Section 5.1.1, Comphy is calibrated to the device electrostatics of each device using the channel material parameters given in Table 5.1. Additionally, as also proposed by Ito et. al [259], fixed positive charges, as given in Table 5.5, have to be used to compensate for the deviation from an ideal device characteristic, c.f. CV measurements in Figure 2.3. It should be noted that the exact origin of these fixed positive charges is subject of ongoing research. In the work of Rescher [193], process splits were performed during device manufacturing and thereby it has been revealed by measuring CV curves after each processing step during the gate stack formation that the poly-Si gate deposition and its subsequent annealing step results in the largest deviations from the ideal CV characteristics. This led to the the hypothesis that the passivation of Si-dangling bonds at the poly-Si/SiO₂ interface in forming gas leads to H $^{+}$ accumulation within the SiO₂ layer and thus to a positive charge build up.

Contrary to the simplex optimization approach used for the lateral devices, the ESiD algorithm is employed to extract defect parameters that can explain the indicated (math image) recovery over the bias and temperature space. As discussed in Section 4.8, a major advantage of this algorithm is that no initial distribution has to be assumed for the defect parameters and respective densities, and thus no initial guess is required. Besides this improvement over the iterative optimization scheme, the computational effort is significantly reduced, as only a few iterations for varying the regularization parameter $\gamma$ , c.f. Figure 4.15 are required. Quite to the contrary, for the bands optimized by the simplex method, the parameter space increases by four parameters, ET and ER mean and standard deviations when assuming Gaussian distributed defect bands, for each additional band. Thus, the optimization in this large parameter space rapidly becomes cumbersome. Here it has to be emphasized that only the application of the ESiD allows to extract defect parameters for the large amount of data acquired by AC and DC MSM schemes with bias and temperature variations. The computational expenses for ESiD are, however, larger than for Si based MOSFETs as an increased defect parameter grid is required due to the AER covering a larger fraction of the entire SiO₂ bandgap. As can be seen in Table 5.6, the parameter grid spanned for the ESiD extraction has been chosen to be split into two layers for electron and hole traps each. The first layer (interfacial layer) spans the range from 0 nm to 0.5 nm from the SiC/SiO₂ interface and is introduced to account for the changing stoichiometric composition and therefore interface defect properties as well as to allow for increased defect densities in the transition region from bulk-SiC to bulk-SiO₂, c.f. Figure 3.3. Additionally, a second layer (oxide trap layer) covering the range of 0.6 nm to 3.0 nm accounts for border traps, as a bulk-SiO₂ property. Note that any further extension to larger distances within the oxide is not meaningful, as the tunneling probability in the transitions rates (4.29) and (4.30) decreases exponentially with increasing distance, as shown in [CST1].

The optimization of the defect parameters by the simulation with the calibrated device and material parameters allows to achieve an excellent agreement between the transient simulation with the measurement data, as exemplary shown for T1/G2 in Figure 5.6. A comparison of the short-term (math image) characteristics is shown in Figure 5.7 by comparing the first point of each AC MSM recovery trace at the different interruption times $t_\mathrm {AC,interrupt}$ . The largest degradation can be observed in T2/G1 for both negative and positive stress bias, as well as for the long-term DC PBTI characterization. More negative ∆V_th at more negative V_G^L can be seen in both T1/G2 and T2/G1, however, negative ∆V_th is not noticeable in T1/G3 at all. The positive (math image) shift values of T1/G3 are well below 0.5 V and slightly smaller than those observed for its preceding technology generation (T1/G2).

5.1.3 Defects Parameters

In order to explain the observed positive (math image) in the lateral test MOSFETs, as well as for all three DMOSFETs, acceptor-like defects in the vicinity of the conduction band edge are required, as the AER spans from $E_\mathrm {c,SiC}$ towards larger energies at PBTI conditions. All technologies therefore show distinct peaks, above $E_\mathrm {c,SiC}$ with varying densities, i.e. NT for electron traps in T2/G1 and lateral MOSFET are about four times higher compared to those in T1/G2 and T1/G3, as can be seen in Figure 5.8 together with their assignments to the employed layers. Also donor-like defects in the lower half of the SiC band-gap are prevalent and distributed over a wide energetic area towards $E_\mathrm {v,SiC}$ , except for T1/G3, which does not require a notable amount of hole traps, consistent with the absence of NBTI in this technology. The extracted relaxation energies are relatively low compared to those extracted for Si-based technologies employing a plasma-nitrided oxide [CSJ8, CSC4].

For the relaxation energies it has to be mentioned that the extracted values in Table 5.4 are considered as too large. This arises from not pinning R to a value of 1 which together with the parameter correlation of R and ER , as mentioned in Section 4.8, leads to the overestimated values for ER . By fixing R to 1 and correcting for the correlation, the mean relaxation energy of the shallow electron trap band reduces to $E_\mathrm {R}$ = 1.82 eV, which is comparable to those for the electron traps extracted in the ESiD spectra with larger ER , shown in Figure 5.8 that are considered as oxide defects. Additionally, the fast EB as well as the ESiD spectra with ER values smaller than 1 eV are associated with interface states, as these defects exhibit significantly smaller ER [208] compared to structures considered for oxide traps [77]. The thermodynamic trap levels of several defect candidates, which have been extracted from DFT calculations found in the literature, are shown in Figure 5.9 together with the AERs for an intermediate stress oxide field of 6 MV/cm, which covers all presented CTLs. It has to be noted, however, that the CTL only represents a thermodynamic property and the charge transfer kinetics depend on the relaxation energy of the defect as well. Also, what is not represented by this graph is the formation energy of the defect candidates, which determines the probability of formation and therefore is correlated to the defect densities in a real device. Finally, the (ET , ER ) maps for the DMOSFETs shown in Figure 5.10 show a strong correlation for the electron traps extracted with two major distributions, i.e. defect types, and in part also for the donor-like defects within the lower half of the SiC bandgap. A possible origin for the different densities extracted for the electron traps with low ER values situated at the conduction band edge is charge trapping at N-complexed defects, as the amount of accumulated N at the interface has been correlated with increasing numbers of interface states at $E_\mathrm {c,SiC}$ [201]. This seems also plausible when considering the fact that N is a suitable dopand with relatively small activation energy in SiC.

$ \mathrm {log}_\mathrm {10}\left (1 + \kappa N_\mathrm {T} / N_\mathrm {T}^\mathrm {max} \right ) $

As the only left “free" parameters in calculating the transition rates (4.29) and (4.30) are the capture-cross sections for electron and hole trapping $\sigma _{n,p}$ , their relevance on the parameter extraction is briefly discussed in the following. Therefore, the impact of a $\sigma$ variation is studied, in steps of one order of magnitude to 1 × 10⁻¹⁴ cm² and 1 × 10⁻¹⁶ cm² [260] from the originally used values of $\sigma _{n,p}$ = 1 × 10⁻¹⁵ cm² [68, 208]. For both alterations of $\sigma$ , the ESiD extraction has been repeatedly applied, with the results shown in Figure 5.11. It becomes evident that the thermodynamic trap level is not significantly influenced by the selection of $\sigma$ , with only minor deviations of the two main distributions around $E_\mathrm {c,SiC}$ . On the other hand, the distribution of ER with larger mean values shifts by about 0.5 eV towards smaller values with decreasing $\sigma$ , while the lower ER distribution is less affected. The change of ER is effectively compensated by the change of charge transfer kinetics due to the altered $\sigma$ value, with no loss in the ESiD accuracy. Even though a large variation of two orders of magnitude in $\sigma$ is shown, the resulting deviation of ER is low, which is a result of the exponential dependence of the rates on ER . As the relaxation energy extracted within the simulation is typically compared to ab-initio calculations, the compensation effect seen between ER and $\sigma$ can be minimized by targeting consistency between the two computational methods.

5.1.4 Temperature Activation of Electron Emission

An non-intuitive feature of the (math image) recovery previously reported by Puschkarsky et. al, is the less pronounced degradation observed for higher $T$ [83], as shown in detail in Figure 5.12. Such an inverse recovery temperature acceleration contradicts observations from NBTI on Si/SiO₂ MOS devices, however, has also been reported for PBTI on n-channel Si/SiON [CSJ8]. As for the Si/SiON technology, in the SiC/SiO₂ device this phenomenon can be explained by a pronounced temperature activation for the electron emission, compared to that for the capture process, which does lead to a higher degradation during the stress phase, as shown in Figure 5.12. For the long-term recovery, a crossover between the recovery curves is observed which leads to larger observable degradation at the higher $T$ after longer recovery times. This phenomena is also well captured by the NMP charge transfer kinetics, with the extracted defect parametrization for the DMOSFETs.

In Figure 5.13 the time to reach ∆V_th= 0.6 V on the lateral devices is plotted for different stress bias and temperatures. The same inverse $T$ behaviour is observed, however, with a strong dependence on the readout time $t^\mathrm {delay}$ and $V_\mathrm {G}^\mathrm {s}$ , as the effect is most pronounced for an intermediate $V_\mathrm {G}^\mathrm {s}$ = 37.5 V ( $E_\mathrm {ox} \approx$ 5 MV/cm), and decays for lower and higher field strengths.

5.1.5 Capture and Emission Time Maps

While the (ET ,ER ) map, c.f. Figure 5.10, represents a full picture of the defect properties, which in turn allows to compute ∆V_th for arbitrary input signals V_G( $t$ , $T$ ), a direct readout of ∆V_th from the map for a specific input signal is not possible. Therefore, Capture Emission Time (CET) maps can be used for a direct representation of the degradation for a specific $V_\mathrm {G}^\mathrm {L}, V_\mathrm {G}^\mathrm {H}$ and $T$ . A large set of experimentally extracted CET and activation energy maps is shown in previous works of Puschkarsky et. al [83, 90, 261]. The main features within these maps are consistent with the previous explanation of a slow and fast degrading and recovering BTI component, transferring into two peaks within these maps. These peculiarities in CET maps extracted from SiC MOSFETs are also prevalent in the lateral test structures, as shown in Figure 5.14 for the experimentally extracted and simulated CET maps.

As a bipolar operation of SiC DMOSFETs is recommended [262] as it increases the long term stability of (math image) , i.e. it reduces long-term BTI, the CET maps of T1/G2 are shown for V_G^L = 0 V compared to V_G^L = −5 V in Figure 5.15. The electron trapping time distributions shift towards smaller $\tau _\mathrm {e}^{L}$ , which leads to the ascribed effect of enhanced electron emission at the fast electron traps, c.f. pulsed MSM in Section 5.1.1. This observation has led to the introduction of preconditioning schemes [87, 88] to primarily measure long term BTI effects.

5.1.6 Reliable Prediction of ∆V_th

The extrapolation of ∆V_th under arbitrary bias and temperature operating conditions is in some works still performed based on fitting a power-law to the measured ∆V_th [263]. However, it lacks of any physical justification, e.g. ∆V_th never saturates, and in the case of SiC MOSFETs even more than one branch of a power law is needed to describe the different regimes of degradation. This fact is emphasized in Figure 5.16 for a constant voltage DC stress bias, leading to a severe overestimation of the degradation. The application of a Gaussian distribution of charge capture and emission times [54] might be justified in the case of only one defect type accounting for the observed ∆V_th, however, in the case of different distributions present, c.f. Section 5.1.4, it leads to an underestimation of ∆V_th. Both empirical methods require in any case different parameters for different read-out delays when measuring ∆V_th. On the contrary, with a carefully calibrated physical defect model, ∆V_th can be predicted for arbitrary input signals and readout delays accurately, shown in Figure 5.16 (right).

A precondition for the calculation of a valid extrapolation of ∆V_th at operating conditions of a MOSFET is the careful design of the stress conditions of the defect parameter extraction. The temperature and stress bias need to be increased to allow to capture charge transition times that are accelerated enough to be shifted into the experimental time window. This acceleration is shown in Figure 5.17 for the harshest PBTI stress conditions (V_G^H = 25 V, $T$ =448 K), which shows a larger defect occupation after the interpolation time of about 100 ks, compared to the occupation after a device lifetime of 10 years at operation conditions (V_G^H = 20 V, $T$ =300 K).

Based on the calibration of the DMOSFET technologies in Comphy, a lifetime prediction is presented in Figure 5.18 for each DMOSFET for different digital AC gate signals, as typically applied, considering a continuous operation. For this, the occupation of the defects has been calculated based on (4.60). It becomes clear that the wide distributions of defects with increased densities for T2/G1 leads to the most pronounced drifts of (math image) , as well as to the largest variation. In contrast, the small densities and absence of hole traps in T1/G3 leads to relatively small drifts during stress, and as low as about 0.2 V only after 10 years, when read out after 1 × 10⁻⁴ µs. Exemplarily shown for T1/G2 is the variation for different (V_G^L,V_G^H) bias combinations with a maximum of about 2 V degradation for unipolar positive bias operation, which refers to the value at the end of the V_G^H phase during the AC period. For all three devices bipolar operation leads to a significantly reduced (math image) shift when an AC signal is applied and readout is performed at V_G $\approx$ .

When comparing the overdrive voltage dependence $V_\mathrm {ov} = V_\mathrm {G} - V_\mathrm {th,0}$ dependence of ∆V_th and on-state resistance shift ∆R_on at different V_G^L, as shown in Figure 5.19, a minimum of about 8 mΩ increase in R_on is predicted after 10 years of continuous operation at the maximum recommended bias conditions. R_on is thereby computed from an initially recorded (math image) ( )-curve with only a small deviation depending on the method of ( ) recording, e.g. continuous sweep or pulsed ( ) measurement, as discussed and shown in [CSJ10]. The continuous ( ) characteristics is used for the R_on calculation in Figure 5.19, as a readout time of 10 µs after the stress phase, as used for the extrapolation of (math image) is expected to compensate for potential accumulation pulses during the pulsed ( ) sweep. With the small static degradation of R_on predicted by the simulation, a minor increase of the static on-state losses $P_\mathrm {on}$ of less than 1 W at continuous current operation at the maximum value according to the datasheet of 10 A can be expected. Finally, in Figure 5.20 the duty cycle $d = t^\mathrm {H} / \left ( t^\mathrm {H} + t^\mathrm {L} \right )$ dependence of ∆V_th shows only a minor variation of about 0.2 V for relevant $d$ in the range 0.1 to 0.9 for all V_G^L, V_G^H permutations, with larger deviations only obtained for the DC operation cases at constant V_G = V_G^L and V_G = V_G^H. This leads to the conclusion that no major deviation due to BTI is predicted for variable high / low voltage conversion operation within a power converter circuit.

5.1.7 Summary

For the first time, BTI in different SiC MOSFETs has been reproduced in detail by a device scale model employing physical defect parameters. The parameters for defects causing the long-term degradation are similar to those extracted in Si-based MOSFETs. However, the obtained defect densities are increased due to the different conduction band offsets in SiC/SiO₂, which enables a larger fraction of shallow electron traps to be charged during device operation. These defects are considered an intrinsic property of SiO₂. Together with fast electron traps, the defects close to the SiC conduction band are a common feature extracted in three commercially available DMOSFETs and a lateral test MOSFET, however, vary quantitatively in the extracted densities. The two components, i.e. fast and shallow EB, have been demonstrated to be separable by accumulation pulses and the optimum operation condition employing bipolar gate drive bias has been explained by the extracted defect charge transition times. These electron trap properties have recently also been confirmed by TCAD simulations employing a detailed four-state NMP model [264]. Furthermore, based on carefully calibrated simulation parameters and including data from accelerated stress experiments, static degradation extrapolation is performed. It predicts that the low on-state resistance and power loss increase can be considered as no major threat in SiC MOSFETs. Although a unique defect candidate cannot be identified with the presented methods, a parameter range is defined in the presented work that can help to further pin down suspected defect structures by single defect characterization in future works.

quantity		ref.	value	unit
$E_\text {G,0}$	band gap at 0 K	[22]	3.36	eV
$E_\text {G,1}$	temperature coefficient	[247, 248]	−3.3 × 10⁻⁴	eV/K
$m_\mathrm {l}$	lateral el. eff. mass	[249, 29]	0.33 $m_\mathrm {e}$	kg
$m_\text {t,0}$	transversal el. eff. mass	[249, 29]	0.42 $m_\mathrm {e}$	kg
$m\sub {a}...m\sub {i}$	coeff. for eff. mass val. band	[33]	see ref	1
$N_\text {cv0}$	band weight	[22]	2.54 × 10¹⁹	1/cm³
$M_\text {c}$	conduction band minima	[22]	3	1
$\varepsilon _\text {r,chan}$	relative permittivity channel	[22]	9.76	1
$\Delta E_\mathrm {w,0}$	channel/gate work. func. diff.	[22]	−1.2	eV
$N\sub {a,chan}$	acceptor doping concentration		2 × 10¹⁷	1/cm³
$N\sub {d,chan}$	donor doping concentration		1 × 10¹⁰	1/cm³

quantity		ref.	value	unit
$E\sub {G}$	band gap		9.0	eV
$E\sub {off}$	channel/oxide $E_\mathrm {v}$ offset	[22]	$-4.68$	eV
$m\sub {t}$	tunneling mass	[250]	0.42 $m_\mathrm {e}$	kg
$\varepsilon _\text {r,ox}$	rel. permittivity oxide		3.9	1
t_ox	thickness of the oxide layer		70	nm

parameter		value	unit
$\Delta E\sub {T}$	trap energy level	0.1	eV
$\Delta S$	relaxation energy level	0.1	eV
$\Delta x\sub {T}$	spatial distribution	0.05	nm
$p\sub {tol}$	cut-off probability	1 × 10⁻⁴	1

parameter	fast EB	shallow EB	HB 1	HB 2	unit
$\overline {E}\sub {T} \pm \sigma _{E_\text {T}}$	$1.87\pm 0.08$	$1.73\pm 0.17$	$-1.12\pm 0.24$	$-1.77\pm 0.04$	eV
$\overline {E}_\mathrm {R} \pm \sigma _{E_\text {R}}$	$0\phantom {.00}+0.85$	$4.93\pm 1.95$	$5.2\phantom {-}\phantom {0}\pm 4.89$	$0\phantom {-}\phantom {.00}+1.55$	eV
$R$	0.9	0.437	1.19	0.6	1
$N\sub {T}$	2.8 × 10¹⁹	3.44 × 10¹⁹	1.26 × 10¹⁹	7.3 × 10¹⁸	1/cm³

Symbol	Quantity	T1/G2	T1/G3	T2/G1	Unit
Q_f	fixed Charge	2 × 10¹¹	1.4 × 10¹²	0	C/cm²
t_ox	oxide thickness	37	33	33	nm

Layer	ET range	$\Delta$ ET	ER range	$\Delta$ ER	xT range	$\Delta$ xT
oxide	−3 eV–3 eV	50 meV	0.1 eV–5 eV	70 meV	0.6 nm–3 nm	0.1 nm
interface	−2.2 eV–2.2 eV	34 meV	0.1 eV–3 eV	70 meV	0.0 nm–0.5 nm	0.1 nm

Modeling of Defect Related Reliability Phenomena in SiC Power-MOSFETs