1.2 Device Fabrication

Semiconductor device fabrication is a process to create ICs present in everyday electronic devices, such as computers, mobile phones, televisions, radios, cameras, washing machines, lights, vehicles, and many more. Fabrication processes are a sequential set of tasks utilizing photolithographic and physical as well as chemical processing techniques during which the 3D IC structures are gradually created on a semiconductor wafer [44]. The processes are performed in highly specialized facilities, known as fabs. The device fabrication process times are very cost-intensive and lengthy, i.e., the entire manufacturing process takes approximately six to eight weeks and can in certain circumstances take up to fifteen weeks [44].

The previously mentioned step-by-step and layer-upon-layer method of producing ICs in a wafer is called planar technology. A big advantage of this technology is that each fabrication step is applied to the entire wafer. Therefore, it is possible to interconnect many devices with high precision and to fabricate many ICs on one wafer at the same time. Thus, from an economical perspective, it is highly beneficial to reduce the area of each IC, i.e., reduce the size of the devices and interconnects, in order to get more chips per wafer and thus reduce costs [44]. For example, over the last decades the node sizes decreased from 10 μm in 1971 to 10 nm in 2017 [45], which is a decrease of three orders of magnitude, meaning that on the same wafer size approximately 106 more chips can be produced via the same process. This development was projected by Moore’s law [46, 47, 48], which states that the number of transistors on a dense IC for the same costs doubles every 18 to 24 months.

The most commonly used processing steps for IC fabrication are photolithography, etching, deposition, ion implantation, thermal oxidation, annealing, and diffusion [44, 49]. The manufacturing steps involved in the fabrication of semiconductor devices are briefly discussed in the following sections. As an example of a device fabrication, simplified processing steps of a SiC MOSFET are schematically depicted in Figure 1.7.

Figure 1.7: Schematic summary of the major processing steps in the fabrication of a SiC MOSFET: 1) p-type SiC substrate wafer, 2) thermal oxidation, 3) photolithography, 4) oxide etching, 5) n+ ion implantation, 6) annealing and diffusion, 7) thermal oxidation, 8) oxide etching, 9) metal deposition, 10) metal etching, 11) dicing and packaging, and 12) final device (left) and device’s circuit scheme (right). D, S, and G stand for drain, source, and gate, respectively.

The fabrication of a SiC MOSFET begins with the SiC substrate wafer, followed by thermal oxidation, photolithography, and etching in order to create a mask for ion implantation. In this way, the oxide is produced selectively, which protects particular areas from ion implantation. The rest of the substrate is implanted with dopants and annealed in order to increase the electrical activity of implanted regions, to repair the crystal lattice, and to reduce the trap density. After that, a high quality oxide is grown on the surface and selectively removed by photolithography and etching to create a gate oxide for the device. Afterwards a metal is deposited and etched on the top and the bottom of the device to create ohmic contacts for the source, gate, and drain. Finally, the device is diced from the wafer and packaged in order to protect it from the external environment and to provide connections to drain, gate, and source for the use in external circuits [1, 49].

1.2.1 Photolithography

Photolithography, also known as optical or UV lithography, is a process to pattern parts of a thin film or the bulk of a semiconductor substrate. It is a photographic process by which a light sensitive polymer, called a photoresist, is exposed and developed to ultimately form 3D relief images on the substrate using a geometric pattern, called a mask [44]. In general, the ideal photoresist image has the exact shape of the intended pattern given by the mask in the plane of the substrate, with vertical walls through the resist. Thus, the final resist pattern is binary, i.e., parts of the substrate are covered with resist while other parts are not. This binary pattern is needed for pattern transfer since the parts of the substrate covered with resist will be protected from etching, ion implantation, or other pattern transfer mechanisms.

The general sequence of processing steps for a typical photolithography process is 1) substrate preparation, 2) photoresist spin coat, 3) pre-bake, 4) exposure to ultraviolet light, 5) post-exposure bake, 6) development, i.e., making photoresist soluble, and 7) post-bake [44, 49]. A resist strip is the final operation in the lithographic process, after the resist pattern has been transferred onto the underlying layer. This sequence is generally performed on several tools linked together into a contiguous unit called a lithographic cluster. In common ICs a modern MOSFET wafer will go through the photolithographic cycle up to fifty times [44].

1.2.2 Etching

Etching is a process to physically or chemically remove layers from the surface of a wafer during device fabrication. In order to generate the desired patterns and geometries on a wafer, several etching steps must be performed before the wafer design is complete [44]. Patterns are controlled via protecting materials which resist etching. Commonly the protective material is a photoresist which is patterned by photolithography (cf. Section 1.2.1).

Etching techniques exist in several varieties, i.e., selective or non-selective and isotropic or anisotropic [44, 49]. If the etching step is intended to make a cavity in a material, the depth of the cavity can be controlled using the etching time and the known etch rate. Many times etching must entirely remove the top layer of a multilayer structure, without damaging the underlying or masking layers. The etching ability to remove one particular material while partly or fully preserving another is selectivity which depends on the ratio of the etch rates for different materials. Some etches undercut the masking layer and form cavities with sloping sidewalls. The distance of undercutting is called bias. Etchants with large bias are called isotropic, because they erode the substrate equally in all directions. Modern processes greatly prefer anisotropic etches, because they produce sharp, well-controlled features [50].

The two fundamental types of etching techniques are liquid-phase (wet) and plasma-phase (dry) etching [44, 49]. The dry etching uses a plasma process where ions and neutral radicals are accelerated towards the surface to remove certain materials. The plasma process is typically anisotropic, where the etch rate is mainly in the direction of the accelerated ions [44]. Wet chemical processes are typically isotropic, i.e., they etch in all directions with the same rate. However, both dry and wet etching can be anisotropic by causing an etch rate variation with different material crystal orientations [49].

1.2.3 Deposition

Deposition is a process that grows, coats, or in any way transfers a material onto the wafer. Various deposition techniques are available today, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layer deposition (ALD) [49, 50]. PVD and CVD are currently the most commonly used techniques in the semiconductor industry.

PVD refers to a variety of vacuum deposition methods which can be used to produce thin films and coatings. It is characterized by a process in which a material changes from the condensed phase to a vapor phase and back to a thin film in condensed phase. No chemical reaction occurs at the deposition site, but rather a material is released from a source and transferred to a substrate [49]. The most commonly used PVD techniques are sputtering and evaporation [44]. Common industrial coatings applied by PVD are titanium nitride (TiN), zirconium nitride (ZrN), chromium nitride, (CrN), and titanium aluminium nitride (TiAlN).

CVD, on the other hand, refers to a chemical process used to produce high-quality and high-performance solid materials. In typical CVD techniques, a wafer is exposed to one or multiple volatile precursors, which react and decompose on the substrate surface to produce the desired deposit. A high deposition temperature is usually required in order to drive the reaction where the resulting film has a very good step coverage and better uniformity, compared to PVD. Industry-related CVD processes include deposition of materials in various forms, such as monocrystalline, polycrystalline, amorphous, and epitaxial [49]. The most common deposition materials are SiO2, C, germanium (Ge), tungsten (W), and titanium (Ti).

1.2.4 Oxidation

Oxidation is a process which generates a layer of oxide, usually SiO2, on the surface of a semiconductor wafer. The oxidation is typically performed at temperatures above 800°C in oxidation furnaces which can accept several wafers at the same time [49]. The orientation of the semiconductor crystal affects the oxidation growth rate as well as the oxide cleanness [1]. An oxide can be either thermally oxidized or chemically deposited [49]. In cases where the oxide must be grown on non-Si-based surfaces, only deposition can be used, because non-Si materials are unable to form SiO2. The chemical deposition is usually performed using tetraethyl orthosilicate or silane pyrolysis [50]. However, the thermal oxidation of any variety is commonly preferred, because it produces a higher-quality oxide with a much cleaner interface, i.e., less interface defects, than the chemical deposition [44].

SiO2 layers of precisely controlled thicknesses are produced during IC fabrication by exposing a semiconductor to either oxygen gas (O2) or water vapor (H2O) at elevated temperatures. In either case the oxidizing species diffuse through the existing oxide and react at the interface, e.g., SiC-SiO2. SiO2 is used for several purposes, ranging from serving as a mask controlling dopant implantation to serving as the most critical component in the MOSFET technology, i.e., the gate oxide [50, 1]. The oxidation process is discussed in more detail in the Chapter 2.

1.2.5 Ion Implantation

Ion implantation is a process which introduces dopants into a material and thereby changes its physical, chemical, or electrical properties. In this process, ions of an element, such as Al, B, P, or N, are accelerated into a solid target like Si or SiC at relatively low temperatures (below 300°C) [44]. Ion implantation equipment typically consists of 1) an ion source, where ions of the desired element are produced, 2) an accelerator, where the ions are electrostatically accelerated to a high energy, and 3) a target chamber, where the ions impinge on a target, which is the material to be implanted. Therefore, ion implantation is considered a special case of particle radiation. Each ion is typically a single atom or molecule. The total amount of implanted material in a target is the integral over time of the ion current, also known as the dose, measured commonly in cm-2 [49].

Dopant ions are generally created from a gas source, for purity reasons, and are afterwards accelerated towards the wafer to penetrate into the crystal lattice. This process generates a charge carrier in a semiconductor for each dopant atom in the lattice [44]. The generated charge carrier can be an electron or a hole, depending on the type of dopants, i.e., donors or acceptors. Doping an intrinsic semiconductor with donor impurities produces n-type semiconductors, which have a large electron concentration after implantation and are negatively charged, thus the term n, which stands for negative. On the other hand, p-type semiconductors are created by doping an intrinsic semiconductor with acceptor impurities and thus have a large hole concentration, and are positively charged, thus the term p, which stands for positive [49].

The crystal structure of a target can be damaged or even destroyed by the energetic collision cascades with ions of high energies. Moreover, the desired carrier concentration is typically not achieved after the implantation, due to defects and clusters which occur during the implantation process. Therefore, post-implantation annealing steps are necessary in order to repair lattice damage and increase electrical activation of the implanted species [1, 50].

1.2.6 Annealing and Diffusion

Annealing is a heat treatment of wafers, which alters the physical and chemical properties of semiconductors. In device fabrication typical techniques are furnace annealing (FA) and rapid thermal annealing (RTA) [44]. Both processes utilize high temperatures (commonly above 1000°C) in order to affect the semiconductors’ electrical and chemical properties, i.e., activate and diffuse dopants, change substrate interfaces, densify deposited layers, change states of the grown films, and repair crystal lattice damage [50]. The main difference between FA and RTA is the timescale of the process, which is in the order of 10-60 minutes for FA and several seconds for RTA. Recently RTA is favored in the semiconductor industry, because the relatively long thermal cycle of FA causes dopants, especially B, to diffuse further than intended. It is important that during the thermal cycles the cooling of wafers must be slow to prevent dislocations and wafer breakage due to the thermal shock [44].

An alternative to ion implantation is diffusion which typically occurs during annealing steps. Charge carriers are introduced into a wafer via the diffusion of dopants from the surface into a semiconductor at relatively high temperatures (above 1000°C). The depth of the diffusion within a semiconductor is a function of the temperature and must be thus carefully executed so that the desired doping profile is not damaged by further processing steps which require high temperatures, e.g., oxidation [49]. One advantage of diffusion over ion implantation is that no damage is introduced to the lattice or the surface, since there is no ion bombardment. Another advantage is the ability to create very shallow and predictable charge concentration profiles. However, for SiC the diffusion of the common dopants is very low and cannot be conveniently used as a doping technique [1].

1.2.7 Dicing and Packaging

Wafer dicing is a process by which the dies, i.e., small blocks of functional circuits on a wafer, are separated from the wafer [44]. The dicing methods include breaking, mechanical sawing, or laser cutting and are typically automated to ensure precision, accuracy, and high throughput. Once a wafer is diced into individual dies, every die is packaged or placed on a circuit substrate [44, 49].

IC packaging is the final stage of the device fabrication, where the tiny blocks of functional circuits, i.e., dies, are each encapsulated in a supporting case which prevents physical damage and corrosion. Packages also include contact pins which are used to connect the produced devices to external circuits, e.g., a central processing unit must be connected to a motherboard [44, 49]. Larger devices, intended particularly for high-power applications, are installed in carefully designed heat sinks so that they can dissipate hundreds or thousands of watts of waste heat produced in a device [50].