List of Figures

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List of Figures

2.1 Chua’s symmetry argument.
3.1 Separated logic and memory units in a two-dimensional CMOS logic system.
3.2 Circuit topology of the TiO $2$ memristive implication logic gate.
3.3 Schematic of the TiO $2$ memristive device cross section.
3.4 (a) $M - V$ characteristics of the TiO $2$ memristor for different values of $w$ . (b) $M - w$ characteristics plotted for a readout voltage of 0.2 V.
3.5 Memristance profile of the TiO $2$ memristive device during a high-to-low resistance switching according to the linear and nonlinear models.
3.6 Modulation of $w S$ and $w T$ during the logic operation for different input patterns.
3.7 $ΔVG$ as a function of $R G$ for different values of $V S,C$ .
3.8 Total state drift as a function of $VS,C$ .
3.9 Cumulative state drift effect in $T$ for State 3.
3.10 Optimized $V SET$ pulse amplitude as a function of the pulse duration (IMP speed) based on the linear and the nonlinear memristor models.
3.11 Average implication operation energy ( $-- EIMP$ ) as a function of the IMP speed based on the linear and the nonlinear memristor models.
4.1 Logic-in-memory architecture and the three-dimensional structure of the magnetic logic circuits.
4.2 (a) DW-TMR memristor structure and its equivalent circuit. (b) A top view of the free layer of a DW-TMR memristor.
4.3 DW-TMR-based implication logic gate.
4.4 Initial current densities passing through the DW-TMR memristor devices $S$ and $T$ as a function of $R G$ .
4.5 $M S$ and $M T$ during the implication operation for different initial logic states (State 1 – State 4) explained in Table 3.2.
4.6 Implication operation energy ( $Ei$ ) as a function of $RG$ in State $i$ .
4.7 The current signals ( $i S$ and $i T$ ) and the DW position ratios ( $r S$ and $rT$ ) of $S$ and $T$ during the implication operation.
4.8 Sketch of basic MTJ structure with a bistable (parallel/antiparallel) magnetization configuration in the free layer.
4.9 Normalized internal state variable of a memristive device as a function of the applied voltage.
4.10 Simplified equivalent circuit of the MTJ SPICE model and the proposed error calculation circuit.
4.11 STT-MTJ switching probability as a function of the applied current based on the modified STT-MTJ SPICE model compared to the decision signal $V1$ from the (unmodified) SPICE model.
4.12 STT-MTJ-based implication logic gates based on (a) the conventional voltage-controlled and (b) the proposed current-controlled topologies.
4.13 AP–to–P switching probabilities of $T$ and $S$ in the CC-IMP gate as a function of $Iimp$ .
4.14 Error probabilities ( $Ei$ ) for different input states of the CC-IMP logic gate as function of (a) $Iimp$ and (b) $RG$ .
4.15 (a) Dominant error probabilities ( $E1$ and $E3$ ) for different TMR ratios. (b) Circuit parameters optimization in the CC-IMP gate with TMR ratio and optimum $RG$ and $Iimp$ of $250%$ , $0.8 kΩ$ , and $0.5 mA$ , respectively.
4.16 Optimized $RG$ in the conventional (VC-IMP) and the proposed (CC-IMP) implication logic gates depending on the TMR ratio.
4.17 (a) The IMP energy consumption and (b) the average error depending on the TMR ratio for both conventional and proposed topologies.
4.18 STT-MTJ-based (a) two-input and (b) three-input reprogrammable logic gates. X $i$ (Y) shows an input (output) MTJ.
4.19 Switching probabilities of the nearest desired ( $P2,3$ ) and undesired ( $P4$ ) switching events shown for the AND (left side) and NAND (right side) operations.
4.20 Average error probabilities for the basic reprogrammable operations as a function of $VA$ .
4.21 Average error probabilities for the implication and two-input reprogrammable logic gates as a function of the TMR ratio.
4.22 Maximum current modulation $(Id - Iu )∕Id$ in implication and two-input reprogrammable logic gates as a function of the TMR ratio.
4.23 Switching dynamics of the MTJ device as function of the applied current plotted for different values of $Δ$ .
4.24 Average error probabilities for the basic operations of the two-input reprogrammable gate (AND, OR, NAND, and NOR) and the proposed CC-IMP gate (IMP) as a function of $Δ$ for $TMR = 200%$ .
4.25 Expectation values of the NIMP error probability ( $--- < ENIMP >$ ) as a function of $Δ$ .
5.1 Common STT-MRAM architecture based on the 1T/1MTJ structure.
5.2 Proposed STT-MRAM-based reprogrammable logic architecture including two common STT-MRAM arrays connected in series.
5.3 Asymmetric 1T/1MTJ-based implementation (right) of the CC-IMP logic gate (left).
5.4 Asymmetric MRAM-based implication logic architecture.
5.5 Bias points of the access transistor in a 1T/1MTJ cell for the selecting (point A) and pre-selecting (point B) voltages applied to the word line of the cell.
5.6 (a) MTJ- and MRAM-based implication logic architectures with no need for a physical $RG$ . (b) Circuit signals for performing the universal NOR operation in MRAM-based implication logic architecture.
5.7 Circuit parameters optimization for minimum error probability of the symmetric implication gate.
5.8 (a) Normalized energy consumption and (b) minimum average error probabilities plotted for MRAM-based implication (IMP) and reprogrammable (Rep.) implementations of some basic Boolean logic operations. The energy is normalized by the TRUE operation switching energy which is equal to 18 $pJ$ for a pulse duration of $t = 50 ns$ in the simulations.
5.9 (a) Normalized energy consumption and (b) minimum average error probabilities plotted for different logic functions.
5.10 (a) Energy consumption for complex logic functions. (b) $--- E f$ for different MRAM-based implementations of functions XOR, half adder (HA), and full adder (FA).
5.11 Coupled MRAM arrays based on the common STT-MRAM architecture suited for parallel MRAM-based computations.
5.12 Logic diagram of a two-bit full adder.
5.13 Required sequential steps for serial (S-IMP) and parallel (P-IMP) MRAM-based implication and combined reprogrammable-implication (CRI) architectures.
6.1 A diagram of the charge-based memristive capacitance sensing circuit.
6.2 A diagram of the memristive power monitoring circuit with a charge-controlled memristor.
6.3 Basic memristor-inductor (ML) circuit for flux-based sensing.
6.4 A diagram of the memristive power monitoring circuit using a flux-controlled memristor.
6.5 (a) TiO $2$ memristor $i - v$ curves. (b) The voltage of the capacitor and (c) the memristance as a function of time. (d) Obtained capacitances by using Eq. 6.4.
6.6 (a) DW-GMR and (b) DW-TMR memristor structures and their equivalent circuits.
6.7 (a) Average domain wall velocity as a function of $i M$ . (b) Final relative domain wall position ( $r$ ) as a function of capacitance.
6.8 (a) Domain wall magnetic thin-film (DW-MTF) spintronic memristor with appropriate geometries for (b) charge-based and (c) flux-based sensing.
6.9 (a) DW-MTF memristor $i - v$ curves. (b) The current flowing through the inductor and (c) the memductance as a function of time. (d) The electric circuit for flux-based inductance sensing and the obtained inductances by using Eq. 6.9.
6.10 (a) Time-varying capacitance and memristive measurement results. (b) The domain wall position and (c) the source voltage $v s$ and the voltage across the capacitor $vC$ and (d) the current flowing through the memristor $iM$ with respect to time.
6.11 (a) Time-varying inductance and memristive measurement results. (b) The domain wall position and (c) the source current $i s$ and the current flowing through the inductor $iL$ and (d) the voltage of the memristor $vM$ with respect to time.
6.12 Proposed DW-MTF memristor structure for simultaneous capacitance and inductance sensing.
6.13 (a) $M (q)$ as a function of charge and (b) $W (φ )$ as a function of flux for the DW-MTF memristor structure shown in Fig. 6.12.
6.14 Time-averaged domain wall velocity (a) in the absence and (b) in the presence of the non-adiabatic spin-torque effect plotted for different geometrical structures ( $ρ$ ).

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