In modern integrated circuits, BEOL (Back End of Line) refers to the entire stack of metal interconnect layers, including wires, vias, and contacts, as well as the insulating dielectric layers that separate them. The BEOL is responsible for the complex routing of signal and power supply lines, enabling the interconnection of hundreds of millions, or even billions, of transistors within a chip.

Since the late 1990s, copper has been the primary material for overall metallization in the BEOL, replacing aluminum due to its lower resistance and improved electromigration (EM) performance. In recent years, however, material choices have diversified further, with ruthenium and cobalt being integrated into the lowest and most critical metal layers (often referred to as nano-interconnects), which are directly connected to transistors. The thickness of interconnects in subsequent metallization layers increases from just a few nanometers in the lower layers to hundreds of nanometers in the upper layers.

Copper remains widely used as the primary metal for interconnects in advanced 3D integration technologies, such as Through-Silicon Vias (TSVs) and Redistribution Layers (RDLs). These technologies enable vertical and lateral interconnections in stacked or packaged devices, supporting high-density and high-performance integration.

Regarding dielectric layers in the BEOL, the original silicon dioxide has been gradually replaced by low-k materials to reduce capacitance and improve performance. Examples include fluorine-doped silicon dioxide (FSG), organosilicate glass (OSG), carbon-doped oxide (CDO), and porous low-k materials.

One of the primary drivers for introducing new materials in the metallization and dielectric components of the BEOL is reliability. Electromigration (EM) remains a significant reliability concern for most metallization types, though ruthenium and cobalt nano-interconnects have shown improved resistance to EM. Other critical reliability challenges include thermo-mechanical stress, thermal dissipation, and stress voiding—especially in advanced structures such as TSVs used for High Bandwidth Memory (HBM) solutions.

BEOL engineering involves using modeling and simulation methods to analyze degradation mechanisms, optimize designs for reliability, and investigate new materials. At the Institute for Microelectronics, a wide range of methods is employed, from density functional-based approaches for atomistic-level analysis to continuum-level methods for the study and predictive simulation of BEOL structures measuring micrometers in size.