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List of Figures

• 1.1. Interface, border and oxide bulk traps. Trap-assisted tunneling is represented by red arrows.

• 1.2. Two competing processes of Si-H bond-breakage: the single- and multiple-carrier mechanisms. The bond is interpreted as a truncated harmonic oscillator.

• 1.3. Disparity between H and D desorption rates induced by electrons tunneling from the STM tip on the passivated Si surface.

• 1.4. The total degradation dose (cumulative N_it as a function of stress time: experiment vs. theory obtained for a 180nm device under worst-case stress conditions, i.e. V_gs = 0.4 V_ds. Inset: distribution of Si-H bond-breakage activation energy.

• 1.5. The interface state concentration N_it, simulation vs. experiment. An n-MOSFET with a gate length of 0.35um and an oxide thickness of 6.5nm was subjected to hot-carrier stress at (1): V_gs = -9V, V_ds = V_sub = 0V; (2): V_gs = 12V, V_sub = 0V and floating source and drain; (3): V_gs = 1V, V_ds= 0V, V_sub= -11V; (4): V_gs = 2.5V, V_ds = 5V, V_gs = 0V.

• 1.6. Different time slopes of hot-carrier induced degradation and NBTI.

• 1.7. The main phases of the reaction-diffusion model applied to NBTI with different time slopes being marked.

• 1.8. The impact of electron-electron scattering on the shape of the carrier energy distribution function. In the former case an additional hump in the distribution function high-energy tail appears.

• 1.9. Schematic representation of the energy-driven paradigm. Knee energies shift depending on the applied voltage.

• 1.10. Experimental bond dissociation rate for the multiple-particle process vs. the theoretical one. The information about stress conditions is shown on the canvas.

• 1.11. Comparison between the experimental device life-time and that calculated within the Bravaix framework (for devices fabricated in a 65nm node).

• 1.12. The flowchart of the proposed model for hot-carrier degradation depicting three main modules: carrier transport module, module for microscopic mechanisms for defect creation, and module for simulations of the degraded devices.

  
  

• 2.1. The electron distribution function for n-type MOSFET at V_ds = 6.5V and V_gs = 2V simulated with and without Multiple Refresh for the same computational time. Graph is taken for room temperature and corresponds to the drain edge of the gate contact.

• 2.2. Experimental (lines) and Non-Self-Consistently simulated (symbols) substrate current of n-type MOSFET with a gate length 0.5um (a) and 2.0um (b) for the series of the drain-source voltage V_ds = 2.0, 3.0, 4.0, 5.0V.

• 2.3. Schematic representation of the considered n⁺pn⁺ structure (above) and 1D doping profile (below).

• 2.4. The electron distribution functions provided by the Spherical Harmonics Expansion and Monte-Carlo (Non-Self-Consistent and Multiple Refresh simulation regimes) approaches. Different letters corresponds to a series of considered position. A rather good agreement confirms the validity of the applied Monte-Carlo simulation schemes.

• 2.5. The simulation flowchart for the carrier transport block of developed HCD model.

• 2.6. The cross section of the high voltage n-type LDMOS transistor (a) before and (b) after the conversion procedure.

  
  

• 3.1. Schematic representation of the SP- and MP-processes.

• 3.2. The topology of an n-MOSFET with the donor doping profile represented by the color map. The origin of the lateral coordinate corresponds to the beginning of the source. Inset: experimental I_ds-V_ds curves vs. simulated ones.

• 3.3. Evolution of crucial characteristics of the degradation with the lateral coordinate: (a) carrier distribution function along the interface; (b) the carrier acceleration integral featuring a peak near the position of most prolonged high-energy tails of the distribution function; (c) the total interface charge density N_it and (d) stored on the SP-related traps N_MP in the region where the AI peaks. I_dlin degradation for (e) different operation V_gs and fixed stress conditions V_gs = 2.0V, V_ds = 7.25V and for (f) different stress V_ds and fixed operation V_ds = 0.1V, V_gs = 5.0V.

• 3.4. (a) The transformation of the transfer characteristics during stress: experiment (symbols) vs. theory (lines). (b) The degradation of the I_dlin current predicted by the electron-only HCD model for different channel lengths.

• 3.5. (a) The average (over the interface length) total degradation dose for different channel lengths.(b) The relative contribution provided by the single-hole component into the total I_dlin change and to the total N_it.

• 3.6. The relative I_dlin change vs. time: experiment, simulations and contributions of electrons and holes separately for channel lengths of (a) 0.5, (b) 1.2 and (c) 2.0um.

• 3.7. The acceleration integrals for electrons and holes for the case of L_ch = 0.5, 1.2 and 2.0um.

• 3.8. The total N_it profile and that induced only by holes for 10s and 10⁴s and for three different channel lengths.

• 3.9. The topology of 5V (a) n-MOSFET and (b) p-MOSFET with the net doping profile highlighted.

• 3.10. Experimental (a) I_sub and (b) I_g as a function of V_gs and V_ds for the n- and p-MOSFET, respectively. Maximum value of the acceleration integral as a function of V_gs and V_dsfor (c) n- and (d) p-MOSFET.

• 3.11. The interrelation between V_gs and V_ds corresponding to the WCC of (a) n- and (b) p-MOSFET. The position of the maximum acceleration integral as a function of V_gs and V_ds for (c) n- and (d) p-MOSFET.

• 3.12. The topology of HV (a) n- and (d) p-LDMOS with the net doping profile highlighted. The interrelation between and V_gs and V_ds corresponding to the WCC of (c) n-MOSFET and (d) p-MOSFET.

• 3.13. The electron acceleration integral calculated with with Monte Carlo, Hydrodynamic, and Drift-Diffusion based versions of the HCD model for the case of (a) L_ch = 0.5um, (b) L_ch = 1.2um and (c) L_ch = 2.0um.

• 3.14. The simulated N_it profiles obtained with Monte Carlo, Hydrodynamic, and Drift-Diffusion based versions of the proposed HCD model for the case (a) L_ch = 0.5um, (b) L_ch = 1.2um and (c) L_ch = 2.0um.

• 3.15. The linear drain current degradation: experiment vs. simulations. The case of (a) L_ch = 0.5um, (b) L_ch = 1.2um and (c) L_ch = 2.0um.

• 3.16. The carrier distribution function: the result of Monte-Carlo simulations and its fitting with the Fiegna model for a long-channel 5V n-type MOSFET.

• 3.17. The maximum value of the acceleration integral as a function of {V_ds,V_gs} calculated with the (a) Fiegna, (b) drift-diffusion and (c) hydrodynamic models.

  
  

• 4.1. Basic experimental setup for charge-pumping measurements.

• 4.2. Definition of (a) local threshold voltage V_th(x) and (b) local flatband voltage V_fb(x) for n-MOSFET. The positive direction of voltage points downwards.

• 4.3. The response of the free carriers to the applied periodic gate pulse. At V_g = V_gh electrons flood into x₁ and holes return to the substrate. At V_g = V_gl electrons return to the drain and holes flood into x₂.

• 4.4. Definition of the effective channel length using the notation of local threshold voltage V_th(x) and V_fb(x) for n-type MOSFET in the case of (a) a constant and (b) a varying amplitude CP technique.

• 4.5. Local threshold V_th(x) and flatband V_fb(x) voltage profiles of a pre-stressed device calculated using different approaches.

• 4.6. (a) Maximum value of the charge pumping current for different gate electrode lengths of the fresh 5V n-type MOSFET. (b) Charge pumping current of an undamaged device. Interface and border trap components are revealed.

• 4.7. The lateral interface state density: comparison of uniform and nonuniform profiles for channel lengths of (a) 0.5 and (b) 2.0um.

• 4.8. (a) The effective channel length determination in the case of constant amplitude charge-pumping current measurement. Inset: charge-pumping current vs. low-level of the gate pulse (V_A = 2V). (b) Maximum value of the charge pumping current for different gate electrode lengths of the fresh CMOS device fabricated on 300mm Si wafers.

• 4.9. (a) Interface state density profile evolution calculated with developed HCD model under assumption of a uniform initial profile and employing N_it(x) extracted according to the proposed scheme. (b) Comparison of the I_dlin degradation calculated with MiniMOS-NT using obtained N_it(x) profiles (a) as input degradation characteristics.

• 4.10. Time evolution of the measured charge-pumping current during hot-carrier stress using the varying high/low-level charge-pumping technique.

• 4.11. The conformal transformation used to solve the gate/drain fringing problem. The complicated case of the corner gate form (red dashed line) is reduced to a ray.

• 4.12. The comparison of equipotential and field-lines in the oxide near the gate corner as the analytical solution and simulated by means of device simulator MiniMOS-NT.

• 4.13. (a) Local threshold and flatband voltage distributions with uniform oxide charge profiles. Inset: the dependence of the oxide thickness vs. the lateral coordinate. (b) The local oxide capacitance calculated using the approach of Lee et al., compared with the newly developed analytical model. Here L_g is the position of the drain end of the gate.

• 4.14. (a) The lateral distributions of N_it(x) and N_ot(x) calculated using different C_ox(x) approaches for 10⁵s at V_ds = 6.5V and V_gs = 2.6V. Peaks of N_it(x) correspond to the maxima of electron and hole acceleration integrals. (b) A comparison of experimental and simulated transfer characteristics for fresh and stressed devices.

• 4.15. Typical local threshold and flatband voltage profiles before {V_th(x), V_fb(x)} and after {V_th,s(x), V_fb,s(x)} hot-carrier stress for n-type MOSFET.

• 4.16. The lateral distributions of (a),(c) N_it(x) and (b),(d) N_ot(x) calculated using different extraction approaches for 10³s and 10⁵s at V_ds = 6.5V and V_gs = 2.6V.

• 4.17. The comparison of the experimental and simulated transfer characteristics for fresh and stressed devices.

• 4.18. The shift of V_th as a function of stress time at various voltages. Inset: ΔV_th measured for devices of the same architecture but different only in channel lengths stressed at V_ds = 6.75V and V_gs=2.0V.

• 4.19. The evolution of N_it(x) and N_ot(x) profiles with stress time for (a) V_ds = 6.25V and (b) V_ds = 6.75V, the gate-source stress voltage was set to 2V.

• 4.20. Filling of the oxide traps revealed for small stress times at the stress regime with V_ds = 6.5V and V_gs = 2.6V.

• 4.21. (a) Time evolution of the measured I_cp-V_gh relationship during hot-carrier stress using the constant-base-level charge-pumping technique. Inset shows the gate pulse train. (b) Local threshold V_th(x) voltage distributions along the channel before and after the stress. The shift of the threshold voltage ΔV_th measured by the maximum transconductance method is shown in inset.

• 4.22. (a) The interface state density vs. coordinate x for several stress times: experiment vs. theory. (b) The position of the maxima of main physical quantities: the electric field, average carrier energy, acceleration integral, position of the most extended tails of the, etc.

• 4.23. The dependence of the acceleration integral for the SP- (solid line) and MP- (dash line) processes. Integrals are given in arbitrary units.

• 4.24. Both (a) SP- and (b) MP-related components of the total interface state density plotted vs. the lateral coordinate.

  
  

• 5.1. An example of a TCAD result for the AI with characteristic activation times being sketched.

• 5.2. (a) A representation of the AI with an analytical expression for various V_ds. (b) The profile of the acceleration integral: comparison between the AI calculated with the TCAD model and the analytical expression.

• 5.3. The parameters A₂, A₃, A₄, β and x₄ vs. V_ds as well as their fitting by the linear dependence on V_ds.

• 5.4. (a) Different contributions to the degradation J_i divided by the gate length for V_ds = 7.25V. (b) I_dlin degradation calculated by substituting one (or some) contribution(s) J_i by the constant value (V_ds = 7.25V).

• 5.5. (a) Comparison between the ΔI_dlin portion induced by the SP-component obtained within the TCAD model and the analytical approach. (b) I_dlin degradation: experiments vs. simulations. Very good agreement between the experimental data and the results of both TCAD and analytical model is obtained.

• 5.6. The AI profiles calculated with (a) the calibrated TCAD model and with (b) the analytical model for different oxide thicknesses (except t_ox, the device topology is identical).

• 5.7. Comparison between AIs calculated with the TCAD model and the analytical expression for two different oxide thicknesses.

• 5.8. Dependences of parameters (a) A₁ and (b) β on the relative oxide thickness t_ox/t_n.

• 5.9. Dependences ΔI_dlin(t) calculated for different values of t_ox.

• 5.10. (a) The mean value of I_dlin(t) vs. t calculated for different σ_d. (b) The standard deviation of ΔI_dlin(t) calculated for different σ_d.

  
  

• 6.1. The evolution of electron AI with stress time for V_ds = 6.5V and V_gs = 2.6V. The position of the N_it(x) peaks does not change with the stress time. The assumption of a constant oxide thickness results in a significant shift of the AI peak for holes and electrons (AI_e(h)→AI_e(h),flat).

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