Erasmus Langer
Siegfried Selberherr
Hajdin Ceric
Johann Cervenka
Siddhartha Dhar
Robert Entner
Wolfgang Gös
Klaus-Tibor Grasser
René Heinzl
Christian Hollauer
Stefan Holzer
Andreas Hössinger
Gerhard Karlowatz
Markus Karner
Hans Kosina
Ling Li
Gregor Meller
Mihail Nedjalkov
Alexandre Nentchev
Vassil Palankovski
Mahdi Pourfath
Philipp Schwaha
Alireza Sheikholeslami
Michael Spevak
Viktor Sverdlov
Oliver Triebl
Enzo Ungersboeck
Martin-Thomas Vasicek
Stanislav Vitanov
Martin Wagner
Wilfried Wessner
Robert Wittmann

Siddhartha Dhar
MSc
dhar(!at)iue.tuwien.ac.at
Biography:
Siddhartha Dhar was born in New Delhi, India, in 1979. He received his B.E. degree in electrical engineering from the Delhi College of Engineering, India in 2001. He then studied microelectronics and microsystems at the Technical University of Hamburg-Harburg, Germany, where he graduated with a M.Sc. degree in 2003. In April 2004, he joined the Institute for Microelectronics, where he is currently pursuing his doctoral degree. His research interests include device modeling and simulation of strained Si CMOS transistors and circuit level simulation in general.

Modeling and Simulation of Strained Si CMOS Transistors

The last several years have witnessed a tremendous amount of research in the area of strained Si, which has the potential to significantly enhance the carrier mobilities in CMOS devices. To design strain-based device structures, it is essential to model the carrier mobilities in this system for different stress/strain conditions. A physically based low-field bulk electron mobility model for Si under arbitrary stress conditions has been developed and implemented into MINIMOS-NT. This model includes valley splitting for a given strain tensor, the effect of reduced inter-valley scattering with increasing splitting in addition to doping, and temperature dependence. Changes in the effective mass due to stress for special stress directions have also been incorporated. The model has been extended to calculate the electron mobilities in strained Ge. Due to the considerable scatter in the experimental data and the ambiguity in the physical explanation of the electron surface mobility enhancement in strained Si, we have abstained from a physical modeling approach and have modeled the surface mobility empirically. The surface mobility strain is assumed to be enhanced by the same factor as the lattice mobility. All these models have been implemented in the general purpose device simulator MINIMOS-NT.
The figure shows a comparison of the simulated effective mobility-field curve for unstrained and biaxially strained Si for various doping levels. Symbols indicate measurement data, and solid lines are simulation results. The effective mobility and effective field have been calculated as explained in the original paper of Sabnis and Clemens. Simulation results show good agreement with the measurement data both for the unstrained and strained case. Electron transport at high-field in strained Si was also investigated using Full-Band Monte Carlo simulations. A strain-dependent empirical mobility model for high electric field has been developed. It describes the velocity components parallel and perpendicular to the electric field as a function of the strain-induced valley splitting. The model is applicable to various technologically relevant strain conditions and has been implemented into MINIMOS-NT. Current work concentrates on simulating novel device structures including distributed stress conditions.


Effective mobility-field for unstrained and biaxially strained silicon for various doping levels. Symbols: experimental. Lines: simulation results.


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