The continual miniaturization of semiconductor devices has been the main driver behind the outstanding increase of speed and performance of integrated circuits. However, active power consumption and leakages continue to increase in scaled devices. The critically high power consumption becomes incompatible with global demands to sustain and accelerate growth within the semiconductor industry, and thus the introduction of new solutions for energy efficient computation becomes paramount.
A highly attractive option to reduce power consumption is to introduce non-volatility in integrated circuits by employing another intrinsic electron degree of freedom: the electron spin. Spin transistors are promising devices where the charge-based functionality is complemented by the electron spin, while the non-volatility is introduced by ferromagnetic source and drain. Tremendous advances in resolving several fundamental problems, including spin injection, propagation, as well as spin manipulation by the electric field, resulted in successful demonstrations of semiconductor spin transistors. However, the relatively small current ratios between parallel/anti-parallel source and drain alignment at room temperature remains a substantial challenge to be resolved in the near future before these devices can enter the market.
In contrast, a magnetic tunnel junction is an excellent candidate for realizing power-reduction, as it possesses a simple structure, long retention time, high endurance, fast operation speed, and yields high integration density. Magnetic tunnel junctions with large magnetoresistance ratios complemented with spin-torque transfer switching are perfectly suited as key elements of electrically addressable non-volatile magnetoresistive memory compatible with complementary metal-oxide-semiconductor technologies and capable of competing with flash, dynamic and even static random access memories.
Regarding active power reduction, delegating data processing capabilities to the non-volatile segment and combining non-volatile elements with CMOS allows for efficient power gating. It also paves the way for a new low-power and high-performance computational paradigm based on an intrinsic in-memory computing architecture, where the same non-volatile elements are used to store and to process the information.