Starting with a plain silicon wafer, many processing steps are necessary to generate a working semiconductor device, with all the desired electrical properties. We are able to sequentially simulate the required processing steps in order to gain a deeper understanding for the physical nature of these processes or to provide realistic structures for device simulations. In our research we combine the atomistic and continuum approaches to enhance our understanding of the physical processes taking place during fabrication, while at the same time providing fast and functional simulation tools which can deal with large-scale problems. Of particular interest to our institute is the study of process variability, where we have investigated the influence of the equipment-induced variation on the process steps and tracked it all the way to the device simulation domain. This way we can link device failures and flaws directly to variations in the equipment used for fabrication.
The main processing steps used in IC fabrication can be summarized as:
A general name given to a series of processing steps which transfer information from a mask onto a wafer surface. First, a photoresist is deposited on the wafer surface and desired areas are exposed to radiation using a photomask. The wafer is then placed in a developer, where the exposed (for positive resists) or protected (for negative resists) sections of the photoresist are removed.
Etching is a semiconductor process used to partially or fully remove materials in order to generate a desired pattern on a wafer surface during fabrication. The main properties of etching are its selectivity and isotropy: selectivity refers to the capability of an etchant to remove one material, while leaving another intact; isotropy is the etchant’s ability to remove a material in multiple directions. The common etching processes are wet, which use liquids to chemically react with the material to be removed and dry, which use a plasma process where ion and neutral species are accelerated towards the surface to be removed and a combination of the physical and chemical interactions on the surface cause the removal of a material. In ViennaTS, we provide state-of-the-art tools for the simulation of wet and dry etching, including complex ion-enhanced plasma etching processes, where deposition of a sidewall polymer and etching takes place concurrently, ensuring a highly vertical etch profile. One application is the simulation of the sequential etching of complex gate stacks in advanced technology nodes, such as the 14nm 14FDSOI node (Fig. 1)
The ability to deposit a new film on a semiconductor wafer is an essential building block for creating insulators, transistor gate stacks, and back end of line interconnects. The deposition processes can be characterized as physical vapor deposition (PVD) or chemical vapor deposition (CVD), depending on the main mechanism used to add a material. The most common PVD processes are evaporation and sputtering, which are usually performed at lower temperatures than CVD, but are not as good at covering trenches, holes, corners, and edges. Within ViennaTS, we have several deposition models implemented, including multiple-species CVD, sputtering, and atomic layer deposition. Recent attempts at forming air gaps as a dielectric materials can be modeled using our in house tools regardless of the number of species involved in the deposition process (Fig. 2).
One of the primary reasons why silicon has become such an important material in the microelectronics industry and in our every-day lives is the relative ease with which it can be oxidized to form an insulating silicon dioxide (SiO2) with good material properties.
This process relies on the interaction with an oxidant species (usually O2 or OH-) at increased temperatures. The thermal oxidation process can be divided into two main mechanisms: dry oxidation, where the wafer is placed in an oxygen gas ambient and wet oxidation, where the wafer is placed in a water ambient. There are ongoing attempts to find new materials which are more scalable than silicon or perform more reliably for high power applications. Any new material must be able to oxidize in order to generate insulating sections. One key feature of our research is the oxidation of new materials such as SiC and III-V materials (Fig. 3).
A semiconductor can be made more conductive by introducing dopants int desired sections, for example to create the source and drain regions of a planar transistor. Ions of a desired dopant material are accelerated in an electric field to impact a solid semiconductor surface. After they penetrate into the top layer of the lattice, an annealing step is performed, resulting in the creation of a charge carrier in the semiconductor layer for each atom in the lattice. The charge carrier can be a hole or an electron, depending on whether the dopant used is p-type or n-type, respectively.
In the context of semiconductor fabrication, annealing is performed after ion implantation in order to redistribute the dopant ions inside the substrate, thereby leading to its “activation”. The annealing step can be used to fine-tune the electrical behavior of a semiconductor layer or to improve the stress performance in a metal line.
The diffusion of dopants from the wafer surface into the semiconductor is an alternative to ion implantation. The dopants can be introduced as a gas, liquid, or from a previously deposited layer; it is only essential that a constant concentration is provided at the semiconductor interface. The depth of the diffusion inside the semiconductor is a function of temperature, so this must be carefully executed so that the thermal budget of the subsequent steps, such as oxidation, do not damage the desired dopant concentration profile. Since subsequent thermal steps influence the dopant profile, simulations are used to calculate for how long a diffusion needs to be carried out and what the influence of the post-diffusion steps will be on the given profile.
This step is used to flatten an irregular wafer surface because imperfections in wafer topology lead to adverse effects in the lithographic process. Modern devices contain multiple layers, which makes it difficult for the photolithographic optical tools to maintain their focus. Applying a CMP step after each deposition step improves material planarity and improves manufacture yield.