Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures


CMOS technology operated at cryogenic temperatures is essential in various fields such as quantum computing (QC), where it serves as a classical control interface for qubits operating in the mK-regime, as host technology enabling a monolithic integration of qubits, or in high-performance computing (HPC) applications. For all these applications, the changing device properties towards cryogenic temperatures must be taken into account in circuit designs. Additionally, potential design optimizations which allow an operation using a very low supply voltage at cryogenic temperatures can be achieved. This is in particular of high interest for QC and HPC to reduce the energy consumption and increase operational frequency. However, the development of robust applications in this field is very challenging for reliability engineers, because their stable operation is very sensitive to drifts of the threshold voltage due to aging and to variability issues. Furthermore, in all applications related to quantum computing, noise originating from charge trapping is very critical, because it can decrease the fidelity of the qubits.

Over the past decades, a deep understanding of the role of defects in the oxide and at the interface between the oxide and substrate has been developed. Such defects can capture and emit a charge which leads to a change in the device electrostatics and are thus responsible for various reliability issues. The charge trapping kinetics can be approximated with the nonradiative multiphonon (NMP) model, which successfully describes the trapping kinetics even at cryogenic temperatures. Since solving the model in its full complexity is computationally expensive, an efficient model has been developed to allow the computation of charge transition rates of thousands of defects and has been implemented in the reliability simulator Comphy. This allows to calculate the cumulative response of many defects and enables a comparison of theoretical trap parameters with measurement data. To this end, bias temperature instability and random telegraph noise (RTN) measurements have been conducted between 4 K and room temperature on various technologies. The degradation behavior has been modeled, allowing the extraction of trap parameters and the identification of defect candidates responsible for altering the device electrostatics.

On large-area devices thousands of such traps can be electrically active simultaneously and the superposition of their responses can be measured. In contrast to that, on scaled devices only few traps are active at the same time, which allows to access properties of single defects. Time-dependent defect spectroscopy and RTN studies which are covered in this work show that there is charge trapping even in the limit of cryogenic temperatures. Charge capture and emission rates become temperature independent towards 4 K which is a consequence of nuclear tunneling. This temperature independence of the trapping kinetics in the deep cryogenic regime has been modeled using the NMP model.

While single devices allow to study the physical device degradation mechanisms in detail, a knowledge of the distribution of device performance parameters is essential to qualify a full technology. For this, the characterization of SmartArrays with thousands of devices which can be addressed digitally has been performed. This allows the study of the variability of time-zero parameters and its dependence on the temperature. An increasing variability of important device parameters towards 4 K can be shown and explained with the occurrence of resonant tunneling which gets more prominent at cryogenic temperatures.