Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

5.2 Investigated MOS Transistor Technologies

With the presented measurement setups the following technologies were used for the characterization of transient curves, random telegraph noise and bias temperature instability between 4 K and room temperature:

  • Technology A: A commercial 28 nm bulk CMOS high-κ technology with a metal gate contact. In a rapid thermal oxidation process a thin interface layer is processed on the substrate. On top a HfO2  high-κ layer is stacked exhibiting an equivalent oxide thickness (EOT) of 1.41 nm. The technology has been used for various characterization methods: Time-zero characteristics have been recorded on large area devices with the dimensions \( W\times L = \SI {10}{\micro \meter } \times \SI {1}{\micro \meter } \) as presented in Section 6.1. The same devices have been used for BTI measurements which are presented in Section 8.2. Scaled devices with dimensions of \( W\times L = \SI {100}{\nano \meter } \times \SI {28}{\nano \meter } \) have been used for variability measurements presented in Section 6.4.1. Devices with \( W=\SI {100}{\nano \meter } \) and different lengths of \( L=\SI {70}{\nano \meter },\SI {100}{\nano \meter },\SI {135}{\nano \meter },\SI {170}{\nano \meter } \) and \( \SI {200}{\nano \meter } \) have been used for variability measurement shown in Section 6.4.2.

  • Technology B: A commercially available 180 nm SiON technology has been used as a simplified system to exclude trapping caused by the high-κ layer. Various device dimensions are available for this technology. Note that for the time-zero characterization the largest available geometry with \( W\times L = \SI {10}{\micro \meter }\times \SI {10}{\micro \meter } \) has been used, see Section 6.1. At this geometry also BTI measurements have been conducted, which are shown in Section 8.2. For the characterization of single defects the smallest available geometry with designed dimensions of \( W\times L = \SI {220}{\nano \meter }\times \SI {180}{\nano \meter } \) has been used, and the corresponding measurement results are presented in Section 7.4.

  • Experimental Batch C: Novel nano-scaled MoS\( _2 \) devices have been fabricated by mechanical exfoliation of few-layer MoS\( _2 \) on 20 nm SiO2 /Si. Using electron beam lithogrphy and plasma etching, the channel was patterned on selected flakes. Afterwards, an evaporation and lift-off process has been used to create source and drain contacts. The device batch was fabricated in a university cleanroom. For RTN measurements presented in Section 7.5 devices with dimensions \( W\times L = \SI {70}{\nano \meter }\times \SI {70}{\nano \meter } \) have been used, and for TDDS characterization presented in Section 8.3 devices with dimensions \( W\times L = \SI {100}{\nano \meter }\times \SI {70}{\nano \meter } \) are selected.