Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

8 Bias Temperature Instability

The effect of bias temperature instability (BTI) occurs, whenever a bias is applied on the gate site of a transistor. The gate bias can reduce or increase the effective energy barrier for a charge transfer reaction between the charge reservoirs and pre-existing or created traps. This process can be accelerated by increasing the temperature, which increases the phonon energy, but also by increasing the applied gate bias. The higher phonon energy leads then to an accelerated energy dissipation of the electron excess energy. This leads to higher charge transition rates via a multiphonon process. BTI degradation has been known since the 1960s [243, 244, 245] and has become one of the main reliability concerns ever since. Historically, NBTI on pMOS devices was the largest concern, however, modern nMOS technologies are eventually affected by PBTI [180].

The charges that become trapped during a stress phase of a BTI experiment have an impact on the device electrostatics, leading to a change of \( \vth \). This perturbation can be approximated using the charge sheet approximation together with an estimate for the active number of traps [199]. When the stress bias is lowered, the defects eventually release the trapped charge. The threshold voltage drift, which has been accumulated during stress by (math image) can recover back to the initial (math image) if it is fully recoverable or otherwise to a constant permanent offset added to (math image). However, separating such a permanent and recoverable part experimentally is difficult which makes the analysis and theoretical description complicated. It is widely accepted that the recoverable component is caused by charge captured at defects in the bulk oxide which can be described with the NMP model [174]. The permanent component can be modeled with an empirical double-well model or, as suggested recently, by considering the depassivation of Si-H bonds which leads to the creation of Pb -centers at the interface [246, 247].

Experimentally, a common approach for the characterization of BTI is using elevated gate bias and temperature conditions for characterizing the shift of the threshold voltage (math image). One widely applied method is the extended Measure-Stress-Measure (eMSM) [248] scheme presented in the following section.

8.1 Extended Measure-Stress-Measure Scheme

For this work, the extended Measure-Stress-Measure (eMSM) scheme [248] is the method of choice for the experimental characterization of BTI. The method consists of three phases and is shown in Fig. 8.1:

  • Phase 1: First, an (math image)((math image)) curve is measured on a pristine device. This (math image)((math image)) curve is used as reference for further (math image) conversion from the measured drain current. For that, it is necessary to identify the (math image) of the transistor which can be done in different ways as discussed in detail in Section 6.1.3. For the characterization of large area devices, typically a constant current criteria is used for the definition of (math image), e.g. \( \vth =\vg (\id =\SI {100}{\nano \ampere }\times W/L) \). For scaled devices on SmartArrays, which show a comparable large variability, a constant current criteria is not practical. Instead, (math image) is defined using (math image). The first phase is shown in Fig. 8.1 marked by (math image)((math image)).

  • Phase 2: After measuring the initial (math image)((math image)) curve, the device is stressed at a well defined condition given by a stress gate voltage (math image) and \( T \) for a stress time (math image). These phases are called stress phases, and are shown in Fig. 8.1 in the red sections. During stress, traps can capture a charge resulting in a decreased drain-source current and an increasing, corresponding (math image), as can be seen in the lower part in Fig. 8.1.

  • Phase 3: The third phase is called recovery phase. It is defined by applying a recovery voltage (math image) for a defined recovery period (math image). During that period, typically the source current \( I_\mathrm {S} \) is measured, because it is more stable against oxide degradation than the drain current \( I_\mathrm {D} \) [248]. The traps, which have captured a charge during the stress phase, can now emit their charge to the reservoir, thus the absolute value of the recovery voltage decreases, as indicated in Fig. 8.1. Typically, \( I_\mathrm {D} \) is mapped to (math image) using the initially measured (math image)((math image)). If the device degradation is fully recoverable, then \( \Delta I_\mathrm {D} \) and (math image) decreases to zero. However, typically a permanent component, which does not decay anymore, is built up and potentially caused by Pb  centers [114].

(-tikz- diagram)

Figure 8.1: The extended Measure-Stress-Measure (eMSM) scheme [248] is used for characterizing BTI. After an initial (math image)((math image)), alternating stress (red) and recovery (blue) phases are applied with defined applied gate voltages (math image) for a defined period. During recovery, the drain currend \( I_\mathrm {D} \) is measured and mapped to (math image) using the initial (math image)((math image)). As indicated in the lower plot and the right figure, during stress (math image) increases, because traps can capture a charge. During recovery, the trapped charge can be released and (math image) partially recovers back to the initially measured value.

Phase 2 and phase 3 are repeated subsequently, which is done typically with increasing stress and recovery times. On large area devices, the measured recovery curves are smooth as they result from a large number of defects which emit their captured charges continuously, as can be seen in Fig. 8.2 (left) for a commercial 180 nm SiON technology node with drawn dimensions \( W\times L = 10 \times \SI {10}{\micro \meter ^2} \) [MJJ2]. On scaled devices it is possible to obtain single capture and emission events as can be seen in Fig. 8.2 (right) on the same technology with drawn dimensions \( W\times L = \SI {400}{\nano \meter } \times \SI {180}{\nano \meter } \) [MJC1]. The measurements on scaled devices build the basis for the time-depend defect spectroscopy (TDDS) [249]. The TDDS is based on the observation that capture and emission times are statistically distributed. By measuring a set of recovery curves with the same (math image) and (math image), the extracted set of step heights and associated emission times can be plotted in a scatter map resulting in a so-called spectral map. The resulting clusters correspond to different defects which allow further investigations of different properties, as discussed in detail in Section 8.3 and in [249].

(-tikz- diagram)

Figure 8.2: The measured drain current \( I_\mathrm {D} \) is continuous on large area devices, because a large number of defects emit previously captured charges simultaneously and the impact of a single defect on the device behavior is too small to be resolved within measurements, as can be seen in the left panel for a \( W\times L = 10 \times \SI {10}{\micro \meter ^2} \) SiON device. On a scaled device of the same technology with drawn dimensions \( W\times L = 400 \times \SI {180}{\nano \meter ^2} \) discrete steps can be seen in the measured current resulting from single charge emission events as shown in the right panel. Figures taken from [MJJ2] and [MJC1].