Cryo-CMOS can be used in various emerging technologies such as in quantum computing as control interface for qubits located at a 4 K stage or as a host technology for a monolithic co-integration of qubits and control instances. It can also be used for high performance computing to increase computational power and to save energy consumption. These applications often require very narrow margins of errors, therefore it is crucial to understand the temperature dependence of MOSFET characteristics to guarantee a high reliability and a low variability of the devices.
All the named applications make use of the changes in the MOSFET () transfer curves towards cryogenic temperatures. Due to the reduced scattering, the charge carrier mobility increases which leads to an increasing on-state current, an increasing transconductance and a steeper subthreshold slope. The temperature dependence of the Fermi levels, the carrier distributions, the band gap and other device properties lead to an increasing threshold voltage. However, in principle the threshold voltage can be reduced by changing design properties, e.g. the processed gate metal or the channel material which allows in combination with the steep subthreshold slope low- operation at cryogenic temperatures. This then enables to increase logic switching rates and thus the performance of the MOSFET. However, low- applications are extremely sensitive to device-to-device variability. In this work, the variability of a commercial planar 28 nm CMOS high-κ metal gate technology is studied on SmartArrays with thousands of devices which can be addressed digitally. This allows to show that the variability of multiple device parameters increases towards 4 K which must be considered in future circuit designs.
In addition, various reliability issues which can arise from electrical stress such as bias temperature instability (BTI), hot carrier degradation (HCD) or random telegraph noise (RTN) have been linked to oxide defects and defects at the interface between insulator and substrate. These defects can capture and emit charges during operation and thus alter the transfer characteristics. The charge transfer kinetics can be described precisely within the nonradiative multiphonon (NMP) model. According to the NMP model, charge transitions between a defect and a charge reservoir are enabled by phonons. While the classical limit of the theory would predict a freeze out of charge transitions, the full quantum mechanical picture allows transitions between atomistic configurations due to nuclear tunneling even at cryogenic temperatures. Since the calculation of the quantum mechanical transition rate is computationally too expensive for reliability simulations, for which typically thousands of defects must be sampled, a WKB-based approximation has been developed which is computationally superior. This model has been implemented in the reliability simulator Comphy which is further used for modeling reliability measurement data.
It has to be pointed out that different reliability issues are dominant across various bias conditions. In this work, the focus has been set on bias temperature instability (BTI) and random telegraph noise (RTN), which has been characterized on various technologies, among others the before mentioned high-κ metal gate technology and a commercial planar SiON technology of a 180 nm technology node. BTI characterization has been performed between room temperature and 4 K for various stress conditions. While on SiON BTI freezes out completely towards 4 K, there is considerably positive BTI on nMOSFETs but no negative BTI on pMOSFETs in the HKMG technology at cryogenic temperatures. This can be modeled using the WKB-based charge transition rate and Comphy by sampling defect bands with different dominant energy levels and relaxation energy distributions for nMOS and pMOS. The occurring BTI degradation at 4 K can be a major reliability concern, specially for low- applications which allow only small margins of threshold voltage shifts. Therefore, BTI shifts must be considered in optimized cryo PDKs and circuits.
While BTI is characterized under elevated stress bias conditions and might be weaker during operation, the impact of RTN cannot be avoided. Charge trapping occurs even at deep cryogenic temperatures due to nuclear tunneling. Towards 4 K nuclear tunneling gets temperature independent, resulting in non-Arrhenius-like transition rates at cryogenic temperatures. By using Comphy, defects at the interface between oxide and substrate have been identified to be responsible for RTN in the commercial SiON technology at cryogenic temperatures. This may be a major concern in solid state qubits and future monolithic designs, because qubits are extremely sensitive to decoherence. Charge noise could cause dephasing and lower the fidelity of the qubits, therefore a deep understanding of the trap kinetics and how to reduce charge noise to a minimum is essential.
The different reliability and variability studies show that charge trapping between atomistic configurations caused by nuclear tunneling is a concern for the stable operation of devices, even at cryogenic temperatures. This is a special concern for potential low- applications which are currently under investigation to reduce power consumption in the cryogenic environment which is essential for quantum computing and to increase logic switching rates for high performance computing. Knowledge gained from the studies presented in this work can further be applied to related fields as the design of solid state qubits, where charge noise caused by oxide defects is crucial for a high fidelity.