Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

1 Introduction

The Digital Revolution goes hand in hand with the rise of the modern semiconductor industry and was enabled by the invention of metal-oxide-semiconductor field-effective transistors (MOSFETs) as the backbones of digital circuits. This would not have been possible without understanding and exploiting effects of quantum mechanics. The development of quantum physics and the resulting scientific and technological breakthroughs in the 20\( ^\mathrm {th} \) century are therefore often called the First Quantum Revolution. Currently, we are in the middle of the Second Quantum Revolution, where devices actively operate with quantum states with the ultimate goal of developing a universal quantum computer [1]. In the following chapter, the role of MOSFETs operated at cryogenic temperatures (cryo-CMOS) and the related challenges will be discussed, setting a special focus on quantum computing (QC) and high-performance computing (HPC). In this context, especially the role of reliability issues in cryo-CMOS devices will be highlighted. The chapter will close by presenting the scope and outline of this thesis.

1.1 Field-Effect Transistor

The Digital Revolution would not have been possible without the field-effect transistor (FET), whose invention started in the early days of the 20\( ^\mathrm {th} \) century. Around 1925, the Austrian physicist Julius Edgar Lilienfeld started to develop the idea and theoretical description on how to use the field effect to modulate the conductivity in a semiconductor triode structure resulting in a patent application in 1928 [2]. Only seven years later, in 1935, the German Physicist Oskar Heil patented the first insulated-gate FET [3]. However, it is unknown whether Lilienfeld or Heil were able to realize a working transistor as proof of concept [4]. From 1948 on developments accelerated when the first junction-gate FET patent was filed by Bell Labs, as suggested by Brattain, Bardeen and Shockley [5]. However, it was not until the 1960s when first MOSFETs where fabricated by Kahng [6] and Atalla [7]. While the first structures suffered from large variations due to a high density of interface defects [8], manufacturing processes improved rapidly and commercially fabricated transistors became available in 1964 by Fairchild and by RCA [4]. Already 1963 the researchers Sah and Wanlass from Fairchild suggested a new type of MOSFET logic combining both nMOS and pMOS, called complementary MOS (CMOS) [9], and filed a patent which was granted in 1967 [10]. This new logic allowed logic circuits operating at significantly lower power consumption and became the de facto standard fabrication process for very-large-scale integration (VLSI) chips in the 1970s. Since then, many improvements of the processing steps, material systems involved and circuit technology enabled to reduce the feature size from the µm-range to a few nm nowadays. For this, the lithography process was improved to enable the fabrication of gate lengths smaller than wavelength of the used UV light. Furthermore, along many other optimizations, new gate and insulator materials such as high-κ dielectrics were introduced and the geometry was improved to non-planar transistors (e.g. FinFETs, GAA FETs).

All these improvements in the fabrication process for manufacturing smaller feature sizes, are summarized in what is today well-known as Moore’s law. In 1965 Gordon Moore, who is a co-founder of Fairchild and Intel, proposed that the number of transistors per chip will double every year [11]. In 1975 he revised this estimation for proposing a redoubling of transistors per chip approximately every two years. This forecast has been followed by the industry for almost 50 years now. However, the scaling of transistors has a natural limit set by the atomic dimensions. The International Technology Roadmap of Semiconductors (ITRS) [12], which sets development standards and outlines future developments, published its final roadmap in 2016, because the classical scaling approach would reach its ultimate limits in the 2020s [13]. Thus, in 2016 the IEEE International Roadmap for Devices and Systems (IRDS) [14] was founded which is the successor of the ITRS and which has a broader focus on future developments. One of the newly defined key topics is Cryogenic Electronics and Quantum Information, which discusses the role of quantum computing as a new emerging field.