Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

9.2 Outlook

In the field of reliability physics, many tools and characterization methods have been developed for getting a deep understanding of the ongoing degradation mechanisms and the responsible defect physics. In this work, the focus is set on BTI degradation and RTN, however, other degradation mechanisms such as HCD, stress induced leakage current or time-dependent gate oxide breakdown have been left out of the picture. Characterizing these degradation mechanisms between 4 K and room temperature would be an enormous step towards a complete overview of the overall trends of reliability issues at cryogenic temperatures.

BTI has been studied in this work mainly on large area devices. By using time-dependent defect spectroscopy, the extension of the characterization to scaled devices could give deep insights in the ongoing charge trapping kinetics at cryogenic temperatures. Charge noise, on the other hand, was mainly characterized in the form of RTN on scaled devices. Since this is quite time-consuming, studying 1/f noise on large area devices between room temperature and 4 K could give a clearer understanding of the overall charge noise trends and its dependence on temperature and bias conditions.

The studies in these work have been done mainly on a commercial planar 28 nm high-κ metal gate technology and a commercial planar 180 nm SiON technology. Repeating these studies on other technology nodes, specially on back-gated FD-SOI technologies, which are in the focus of many research groups, could deliver a valuable input regarding the impact of the device design on the reliability. In the case of back-gated FD-SOI devices the impact of the back-gate bias on BTI degradation, charge noise and device-to-device variability could be studied.

The access to experimental low-\( V_\mathrm {DD} \) MOSFETs, which are specially optimized for cryogenic applications and do not work at room temperature, would allow almost infinite possibilities for reliability studies. The performance in terms of reliability of such structures is unknown yet. However, due to the minimized \( V_\mathrm {DD} \) the structures might be very sensitive to variability and threshold voltage shifts, therefore detailed studies of the known degradation mechanisms are of a very high interest.

The knowledge of defect physics in the context of MOSFETs at cryogenic temperatures could also be applied to qubit structures. Since qubits are complicated structures with multiple oxide layers, charge trapping kinetics of defects in these oxide layers could be very similar to the kinetics in MOSFETs. Studying the technology used for qubits could give important insights how to reduce charge trapping, which is a main concern for stable operation, because it can lead to decoherence and dephasing of the qubits.