Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

1.3 Reliability and Variability Issues in Cryo-CMOS

By operating devices at cryogenic temperatures, new challenges for CMOS engineering arise. Performance and device characteristics are strongly affected by the operation temperature and models developed for room temperature and above considerably loose in accuracy at low temperatures. Therefore, a large effort was put into the development of cryogenic models for transfer characteristics [109] and derived quantities as subthreshold swing [110], threshold voltage [111], on-state current [112], etc. While the proposed models steadily improve, reliability issues are rarely addressed. However, the stable operation can be affected by a wide range of stress mechanisms, for example caused by radiation, heat, mechanical or electrical stress. These diverse stress mechanisms can have an impact on the transfer characteristics by reducing the performance, increasing leakage currents, or leading in the worst case to a complete oxide breakdown.

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Figure 1.6: A schematic representation of the \( \{\vg ,\vd \} \)-space shows the dominating degradation mechanisms for the different bias regimes.

Device aging is inevitable during regular operation, thus, a highly stable dielectric layer is an important building stone for meeting the lifetime-criterion of electronic circuits. Therefore, the focus of this work will lie on aging mechanisms caused by electrical stress, and the impact of this stress on pre-existing or generated defects in the MOSFET oxide. These defects can capture and emit a charge and thus affect the transfer characteristic of devices. Oxide defects and defects at the interface between oxide and substrate can not only occur in transistors, they can also disturb the stable operation of quantum dots. As discussed in the previous section, QDs are complex structures with multiple oxide layers. Since reaching a high fidelity is one of the main challenges in the engineering of qubits, guaranteeing high quality interfaces between substrate and these oxide layers is essential to avoid charge trapping.

For understanding the mechanisms of charge trapping, it is necessary to differentiate between various degradation mechanisms, which will be dominant at different bias conditions as can be seen in Fig. 1.6

  • • Bias temperature instability (BTI): BTI occurs, whenever a bias is applied on the gate side of a transistor. The applied bias reduces the barrier between the charge reservoir, which can be either the channel or the gate, allowing the traps to capture charge. The trapped charges then affect the electrostatics and consequently change the device transfer characteristics. On large-area devices, this can be seen as a continuous shift of the threshold voltage, caused by thousands of defects capturing and emitting charges simultaneously when the threshold voltage is monitored over time. By scaling the geometry of a transistor, discrete steps can be seen in the measured current, which reveal single charge capture and emission events. To examine this effects, typically elevated temperatures and voltages above the operational condition are used to accelerate the degradation. Since elevated temperatures do not make sense for the study of BTI in cryogenic environments, studies in this work will often be based on elevated voltage conditions. Also, it has to be noted that generally BTI is classified into negative BTI (NBTI) and positive BTI (pBTI), determined by the sign of the gate voltage applied during the stress, which can be measured on both nMOS and pMOS. However, typically the focus lies on NBTI on pMOS devices and PBTI on nMOS devices corresponding to the typically used bias conditions. A more detailed introduction to BTI can be found in Section 8 and in [113, 114, 115].

  • • 1/f noise and random telegraph noise (RTN): Oxide defects can exchange charges with the device substrate or the gate, even under non-accelerated conditions. The ongoing mechanisms are the same as in BTI, i.e. defects can capture and emit charges, altering the device electrostatics and leading to fluctuations in the device parameters. However, in contrast to BTI, less defects can contribute to the noise. But similar to BTI, while on large-area devices the fluctuations are continuous and known as 1/f noise, there are discrete steps on scaled devices, which are known as random telegraph noise (RTN) [116, 117, 118].

  • • Hot carrier degradation (HCD): Compared to BTI which focuses on elevated gate insulator fields while no drain-source bias is applied to result in a uniform carrier distribution along the channel during stress, HCD describes the degradation under non-equilibrium conditions, i.e. at accelerated drain bias conditions. A high drain-source field accelerates the carriers to either drain or source (depending on the carrier type) leading to carriers with a high kinetic energy. These so-called hot carriers cause damage in the channel or at the Si/SiO2  interface where they can create interface defects which can capture and emit charges. However, unlike BTI, the damage caused by the high energetic carriers is mostly irreversible. A more detailed overview to HCD can be found in [119, 120].

The above mentioned degradation mechanisms have been well studied over the past decades and a profound knowledge has been gained on how the behavior of MOSFETs is affected in various ways. In addition, the community of defect physics has made lots of progress in understanding the role of defects in MOSFET degradation, and fundamental theories like nonradiative multiphonon (NMP) theory have been established to describe the interaction of defects with charge reservoirs, as will be discussed in detail in Section 3. While there are innumerable reliability studies on reliability issues in electronics in above room-temperature environments, there is a lack of degradation studies in cryogenic environments. However, with the ever increasing interest in QC the research for robust electronic systems operated in cryogenic environments becomes increasingly important. As one part of it, the gained knowledge from defect studies at cryogenic temperatures helps developing devices operating stably in such environments. This is of special importance, because many cryogenic applications are extremely sensitive to reliability issues. As discussed, the classical control interface of quantum computing should be as close as possible to the qubits and thus at the cryogenic stage. At the same time, qubits are extremely noise sensitive, therefore charge noise must be reduced as much as possible in the CMOS control interface. This gets even more critical in monolithical qubits, where the CMOS control unit is as close as possible to the qubits. Here, charge noise is very likely to accelerate dephasing of the qubits and can therefore have a negative impact on the qubit fidelity.

Reliability issues play a crucial role in high performance computing. A low-\( V_\mathrm {DD} \) is important for electronics in HPC to increase the logical switching rate and to decrease the total power consumption. However, it comes with the price that circuits become very sensitive to variability. A large variability of the devices has the effect that a switching between on- and off-state can not be guaranteed anymore within low-(math image) applications. Additionally, small (math image) shifts can already disturb the stable switching and thus compromise a reliable operation. Therefore, it is essential to include variability and reliability considerations in design of optimized CMOS applications [121].

Knowledge on defect physics gained from reliability studies on cryo-CMOS applications can be further used in related fields. Since cryogenic environments are often used to reduce noise, charge noise caused by oxide defects or by interface defects between the numerous different processed layers (see Fig. 1.3 (c)) is a major concern for qubits. In the qubit design, one of the main engineering challenges is reaching a high fidelity and avoiding decoherence. Defects which get created during device manufacturing can affect the readout of the spin in superconducting qubits [122, 123, 124, 125] or have an impact on the confinement of the QD forming the electron spin qubits causing dephasing [78, 126, 127, 128, 129, 130, 131, 80, 132]. Therefore, understanding the physics of the occurring traps from theoretical calculations [133, 134, 135] and from experiments as shown in this work can deliver a valuable contribution in reducing the loss of decoherence in solid state qubits.