Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

7.4 RTN in SiON Devices

In the following section RTN measurements on Tech. B are presented. While for the time zero characterization large area devices with have been used, scaled devices with are used for the presented noise analysis. A set of both nMOS and pMOS devices with this geometry has been scanned to find transistors with active RTN defects. In total 3 nMOS devices (defect A-C) and 1 pMOS device (defect D) with RTN signals which could be followed over a range of gate voltages and temperatures have been found. The analysis of the measured signals was performed using the Canny edge detector discussed in Section 7.3.1.

7.4.1 Temperature and Gate Voltage Variation

An ideal measurement can be seen in Fig. 7.6 (the good) for a nMOS device at and . The steps can be easily detected with the Canny edge detector, as indicated with the red lines. The extraction of the step heights shows two Gaussian distributions (, ) and the capture and emission times are exponentially distributed. However, these ideal conditions are only observed for a rather small measurement window. When sweeping over a large set of gate voltages, for higher and lower voltages the charge transition times become very small or very large. This has the effect that the signal shows extremely narrow peaks as can be seen in Fig. 7.6 (the bad), again at but at a higher gate voltage of . These sharp peaks still allow a reasonable extraction of the step heights, as can be seen in the Gaussian distributions (, ). However, the extraction of the capture times  is limited by the measurement resolution and thus the exponential distribution shows a cut off. While these truncated signals still allow to extract useful parameters, this becomes difficult at higher temperatures. At in Fig. 7.6 (the ugly) one can clearly see the remains of the clear RTN signal seen before, however, a parameter extraction has become impossible. Nevertheless, across a certain temperature and voltage range it is possible to follow the defects and to extract step heights, capture and emission times.

The scan across temperatures and gate voltages can be seen in Fig. 7.7. At every set of it is possible to extract a capture time  (red) and an emission time  (blue), as can be seen for for  between and . The capture time shows a strong gate voltage dependence, whereas the emission time is almost  independent, as known from other technologies [114], however, both can be fitted linearly on the log-scale. These linear fits for  and  intersect at the gate voltage where . At this  the trap level is aligned with the semiconductor Fermi level and it will be used later in this section to study the -dependence of the corresponding transition times.

Extraction of Step Heights

As shown in the previous section, the distribution of step heights can be extracted for every signal at a certain and . By extracting the means of these typically Gaussian distributions it is possible to find the and  dependence of the mean step heights . The gate voltage dependence of  for different temperatures can be seen for defect and defect in Fig. 7.8. For nMOS, the mean step heights decrease with increasing . This can be attributed to the fact that the channel uniformity increases with increasing  and thus the impact of a single charge on the drain-source current decreases [240]. This mechanism is temperature independent, as can be seen in the figure. The same observation holds for pMOS, where with decreasing  the step heights decrease, as can be seen for defect in Fig. 7.8.

Using the extracted ,  for different  in Fig. 7.7, it is possible to compute the interpolated  at the point where . This can be done for a range of temperatures to obtain the dependence of . Again, it can be seen that the step height is nearly temperature independent in this cryogenic temperature range.

Extraction of Average Capture and Emission Times

For the analysis of the and  dependence of the average capture and emission times  and , again the extractions as shown in Fig. 7.7 are used. Now, in Fig. 7.9 the average times are shown in a more compact way with all measured temperatures in a single plot for defect A and D. Within this single plot it can be clearly seen that the measured  and  curves shift towards faster capture and emission times with increasing temperatures.

The marked stars in Fig. 7.9 where holds can be plotted in an Arrhenius-plot, see Fig. 7.10. It can be seen that the charge transition times become temperature independent at cryogenic temperatures in both nMOS and pMOS devices. This temperature independent regime can be modeled using Comphy with the implemented quantum mechanical transition rates, as discussed in detail in Chapter 3. The solid lines, representing the simulation, show that nuclear tunneling explains the temperature independent behavior of charge trapping at cryogenic temperatures, whereas the classical model (dashed lines) freezes out completely. Nuclear tunneling at cryogenic temperatures is dominated by the overlap of the ground vibrational states of the initial and final states. These ground states are occupied, even at 4 K, and enable charge transitions.

The simulation allows to find a pre-existing defect with a parameter set of trap level , relaxation energy , configuration coordinate offset , and position in the oxide  which describes the measured temperature dependence of the charge transition times of the RTN signal. The extracted parameters for every defect are listed in Tab. 7.1.

Defect	Device	[eV]	[meV]	[nm]	[]	[meV]
Defect A	nMOS	0.44	110	0.2	3.5	28
Defect B	nMOS	0.48	95	0.3	3.0	24
Defect C	nMOS	0.46	60	0.05	2.6	15
Defect D	pMOS	-0.48	100	0.25	3.0	25

Table 7.1: The extracted temperature dependence of the charge transition times allows to extract trap levels, relaxation energies, spacial positions and configuration coordinate displacements of defect candidates for the measured RTN signals.

The extracted spatial and energetic position are shown in Fig. 7.11. As can be seen, the electrically active defects on nMOS (left) are close to the conduction band edge. The active defect in the pMOS device, on the other hand, is close to the valence band edge of the substrate. This energetic alignment guarantees charge transition times with . The spatial position of all defects is less than 0.5 nm from the Si/SiO2  interface. This, together with the trap level alignment strongly indicates that the defects responsible for RTN in cryogenic environments are interface defects.

This idea can further be supported by DFT calculations. The regions marked as oxide defects in Fig. 7.12 are extracted from [MJJ2]. The extracted  and  parameters are in good agreement for possible oxide defect candidates [MJJ2]. The ellipsoid formed region marked as interface defects within the Si bandgap is extracted from [142]. It shows that interface defects are expected to have low relaxation energies compared to oxide defects. The colored circles represent Defect A to D discussed in this section. As can be seen, the extracted values are in good agreement with the DFT calculations for interface defects, which are highlighted in Fig. 7.12.