The characterization of time-zero properties is central for determining the performance of transistors. This characterization is typically done on single transistors using probe stations with manual needle arms. Using this approach,
the collection of a large set of measurement data is extremely time consuming and makes variability studies unfeasible. However, a small variability is, specially for cryogenic applications which typically use a very low , inevitable. Therefore, a different approach is used based on *SmartArrays* with thousands of transistors which can be addressed individually as explained in detail in Section 5.3. This allows to conduct measurements on thousands of pristine devices efficiently and to characterize the variability and mismatch of
DUTs between 4.2 K and room temperature.

*SmartArray A* and *SmartArray B* were characterized by Alexander Grill and the author of this thesis during research visits at *imec* in 2019 and 2021, respectively. Measurement results have been
published in [MJC3, MJC5].

*SmartArray A* consists of twelve Blocks with 2 560 transistors per block, in total 30 720 transistors of *Tech.
A* with , and is described in detail in Section 5.3. For the variability study, for each temperature of the set two blocks of pristine nMOS devices (5 120 transistors) have been characterized. For this, transfer characteristics between and have been recorded in the linear and saturation region using and , respectively.

The recorded transfer characteristics in the linear region are shown for RT and 4 K in Fig. 6.11 (a,c). The red arrows in the subthreshold region indicate that the variability increases towards cryogenic temperatures. This holds specially true in the subthreshold regime. The same can be observed for the transconductance in Fig. 6.11 (b,d). Also for the variability increases towards 4 K. The variability has a maximum at the same , at which has a maximum.

An increased variability in the subthreshold region has been reported before [228, 229]. Typically, it is attributed to resonant tunneling caused by surface roughness, defects or dopants. The resonance leads to humps in the transfer curves or to a double threshold behavior and therefore massively increases the variability [MJC3, MJC5]. The role of resonant tunneling is discussed in more detail in Section 6.3. The four selected transfer lines from this measurement set in Fig. 6.9 (left) show clearly how resonant tunneling affects the variability.

The variability of , , and extracted from the recorded transfer curves in the linear region can be seen in the quantile plots in Fig. 6.12 (a,b,c,d), respectively. A significant increase in the variability towards cryogenic temperatures can be seen only for . , and show the well known temperature dependence discussed in detail in Section 6.1, however, the variability stays approximately constant. The measurement at 300 K shows an offset which can be most likely attributed to leakage stemming from broken devices.

The quantile plots in Fig. 6.12 correspond to the main diagonal in the correlation plot for the linear regime in Fig. 6.13 (top). The correlation plot in Fig. 6.13 (bottom) corresponds to an equivalent measurement set in the saturation region. While shows a strong variability increase in the linear region, the variability is rather constant across all temperatures in the saturation region. The same holds true for , and .

The histograms above the main diagonal show a strong negative correlation between and in both the linear and the saturation region. This can be explained by the fact that is defined using but is defined at a constant voltage instead of a constant overdrive. The strong positive correlation between and is caused by the effect that both are strongly affected by the increasing mobility. Both correlations slightly decrease towards cryogenic temperatures. This could arise from mobility saturation, but also from other effects like the more dominant contact resistance at 4.2 K [MJC5]. The leaking measurements can be clearly seen in the scatter plots below the main diagonal, where the cloud at 300 K shows a clear offset.

In essence, the same relations as in the correlation plots can be seen in the mismatch plots for the linear region and the saturation region in Fig. 6.14 (top) and (bottom), respectively. The parameter mismatch is defined by the difference of a parameter of two neighboring devices, e.g.

This definition takes both pairs and into account.

As shown before in the correlation plots, the histograms above the main diagonal show strong correlations between and and between and . The variability of the mismatch is slightly higher at cryogenic temperatures compared to RT, as can be seen in the main diagonals. This effect is most dominant for the mismatch of . The offset in the measurement at 300 K cancels out in the mismatch plot.

For the set of measured transfer curves, mean , , and can be computed. As can be seen in Fig. 6.15, the mean values for both the linear and the saturation region show the same behavior discussed for large area devices in Section 6.1. The mean shows the typical saturation towards cryogenic temperatures, which is explained by band tail states, see Section 6.1.1. The mean and increase at lower temperatures due to the increasing charge carrier mobility caused by less phonon scattering, as discussed in Section 6.1.2 and 6.1.4. The bars showing the confidence interval of one-sigma clearly show the increasing variability of . The increasing and show a slight saturation behavior, which again can be explained by band tail states.

*SmartArray B* exists in two variations, either with 2 500 nMOS or pMOS transistors of *Tech. A*. All transistors have
a width of , while there are sets of 500 devices with lengths . A detailed description of *SmartArray B* can be found in Section 5.3. For every set of dimensions,
transition curves have been recorded for the temperatures , and in the linear region using and in the saturation region using .

The recorded transfer curves are shown in Fig. 6.16. For both the linear and the saturation region and across all gate lengths the () curves shift and get steeper towards 4.2 K, as is well known from large area devices and discussed in detail Section 6.1. The transfer curves shift to higher gate voltages with increasing lengths, as it is well known from literature. The ()-curves show a large asymmetry between nMOS and pMOS, which is not predicted by the PDK. The reason for that is still debated.

Using the recorded transfer curves in Fig. 6.16, the transconductance can be derived for all drawn dimensions and measurement regimes, as can be seen in Fig. 6.17. The curves show clearly, that the variability in increases towards cryogenic temperatures. The maximum variability is in the same gate voltage region as . Moreover, it can be seen that the variability increases towards larger device dimensions. The asymmetry in the transfer curves propagates to the transconductance, leading to a in nMOS devices which is approximately by a factor 0.5 larger than in pMOS devices. The point of the maximum transconductance of the devices with is in the saturation region very close to the edge of the measurement window, or even outside of the window. This makes a further analysis of derived parameters difficult.

As it has been done before for *SmartArray A*, the recorded set of transition curves allows to analyze the correlation and mismatch of , , , and for every used dimension. Exemplary, correlation and mismatch plots for nMOS and pMOS in the linear region are shown in Fig. 6.18 for the smallest geometry . The variability for both nMOS in Fig. 6.18 (top) and pMOS in Fig. 6.18 (bottom) behave similar as for *SmartArray A*. The strongest variability increase towards cryogenic temperatures can be seen in . However, there is also a variability increase in and in , as can be seen in the quantile plots in the main diagonal. As observed before for *SmartArray A*, there is a strong negative correlation between and , which can again be explained by the definition of a constant . The strong positive correlation between and is caused by the strong dependence on the mobility of both parameters. Towards cryogenic temperatures the correlations decrease slightly, which may be explained by relatively stronger contact resistance. The
same observations can be made for the variability of the pMOS devices with .

The same overall trends can be observed in the mismatch plots for nMOS in Fig. 6.19 (top) and pMOS in Fig. 6.19 (bottom). The parameter mismatch, which is defined as the difference in a certain parameter of neighbored transistors shows the strongest variability increase in . There is also a strong variability for the lowest measured temperature in . The strong correlations between and and between and have been observed before in the correlation plots and are caused by the same mechanisms.

The recorded transition curves in Fig. 6.16 allow not only the analysis of the variability but also of the impact of dimension and temperature
variation on the mean , , , and as it can be seen in Fig. 6.20 and 6.21 for
nMOS and pMOS, respectively. In both, the linear region and the saturation region the parameters listed earlier have been extracted for transition curves on all 500 available transistors per geometry on *SmartArray B*. This
has been done for and 300 K. The extracted mean values are represented with a confidence interval of one-sigma. The increasing confidence intervals towards cryogenic temperatures for are in agreement with the correlation plots in Fig. 6.18.

The trends of the mean values are in agreement with the trends measured on large area devices in Section 6.1 and on
*SmartArray A*. As expected, mean and mean increase for nMOS and decrease on pMOS towards cryogenic temperatures due to the increasing mobility. shows a saturation in the saturation region while shows a saturation for both conditions. Smaller gate lengths result in a larger and as expected from basic MOSFET theory. The well studied -saturation caused by band tail states is more distinct for the pMOS devices than for the nMOS devices, specially in the linear region. Conspicuously, shows a small dependence on the geometry on pMOS unlike the nMOS devices, on which the drawn dimensions have almost no influence. increases on nMOS and decreases on pMOS towards 4.2 K. The saturation effect which is specially observed on the nMOS devices can be explained by band tail states [111]. As expected from theory,
shorter channels lead to a smaller threshold voltage [205].