Charge Trapping and Variability in CMOS Technologiesat Cryogenic Temperatures

1.2 Cryo-CMOS Applications

As Moore’s law reaches its limits with respect to scaling the transistors on the chips, it is necessary to develop Beyond CMOS technologies [14]. Beyond CMOS as it is defined by the IRDS spans a wide range of research fields, such as carbon nanotube FETs, graphene based devices, molecular electronics, spintronics, optical computing, or superconducting computing [14]. The most prominent application of the latter, is superconducting quantum computing. Various approaches for building a quantum computer (including the superconducting approach) need cryogenic environments, which have made cryo-CMOS an emerging field in the past years. However, cryo-CMOS has also multiple other potential applications, such as high-performance computing [15, 16, 17] or space technologies [18]. Quantum computing (QC) and high-performance computing (HPC) will be introduced in more detail in the following, because these are central cryo-CMOS applications in the Beyond CMOS program of TU Vienna’s research partner imec.

1.2.1 Quantum Computing

With the First Quantum Revolution in the early 20\( ^\mathrm {th} \) century, a range of technologies which determine our daily lives nowadays emerged. Electronics, satellites, lasers, medical imagery, etc. would not have been realizable without a deep understanding of quantum mechanics. Now, for the Second Quantum Revolution, global players invest billions for research and development of new technologies. In its \( 14^\mathrm {th} \) 5-Year-Plan for 2021 to 2025, China declared quantum technologies as a key technology [19]. Within the Quantum Flagship project started in 2018 [20], the European Union invests at least 1 Billion Euros in the research on quantum technologies with the ultimate goal of developing a quantum computer (QC) that is able to outperform classical computers in certain tasks. But not only governments invest Billions into QC, also private technology companies see a potential market and already demonstrated a QC on small scales, e.g. Sycamore from Google [21], IBM Q [22] or Quantum Inspire from Intel/QuTech [23]. An overview of the largest QC projects is given in Fig. 1.1.


Figure 1.1: First proof of concepts for QC were shown around the turn of the millennium [24, 25, 26, 27]. Different approaches are under development for universal quantum computers (UQC): Superconducting qubits: IBM [28], Rigetti [29, 30], Intel [31], Alibaba [32], MISIS [33], Transmon qubits: Goolge [34, 35, 21], Rigetti (Project Acorn) [36], Electron spin qubits: QuTech/TU Delft [37, 38, 23], Trapped Ions: IonQ [39, 40], Honeywell [41, 42, 43], Photonics: Xanadu [44, 45], USTC [46, 47]. Quantum annealing systems, which are not UQC, are commercially available since 2011 [48, 49, 50, 51]. The goal announced by Intel and Google is a UQC with 1 million physical qubits by 2030.

While classical computers can solve problems from the complexity class BPP (bounded-error probabilistic polynomial time) with efficient probabilistic algorithms, QCs can access the complexity class BQP (bounded-error quantum polynomial time) and can thus solve certain problems very efficiently, which are not accessible for classical computers within a reasonable computation time [52]. This class of BQP problems occurs in various fields such as cryptography [53], machine learning [54], medicine [55], computational chemistry [56] or in the financial sector [57], and thus attracts a large interest from different stakeholders in industry and research alike.

QCs are based on the fundamental concept of quantum bits (so called qubits), the basic units in quantum information technology, which are analogous concepts to binary bits, which are well known from classical computers. Mathematically, a qubit is a linear combination (superposition) \( \alpha \ket {0} + \beta \ket {1} \) of two orthogonal basis vectors \( \ket {0} \) and \( \ket {1} \). This superposition is typically represented by a Bloch sphere, as can be seen in Fig. 1.2 (left). By using qubits, it is possible to build quantum logic gates, the basis of quantum circuits [52]. A single-qubit gate operation can be represented by a \( 2\times 2 \) unitary matrix having the effect of a rotation of the Bloch vector on the spherical surface. While the mathematical description of single qubits is rather simple, the engineering task of building physical qubits is still extremely challenging. Since qubits use fundamental properties of quantum mechanics, such as superposition and entanglement, they also suffer from decoherence. Decoherence can be interpreted as an irreversible information loss of quantum states as soon as there is any type of interaction with the environment. To minimize this interaction, qubits are operated at cryogenic temperatures. Despite the many difficulties for the operation of qubits, there have been first major successes. The QCs of Google, IBM, and Intel/QuTech operate between 50 and 100 qubits and successfully run some simple quantum algorithms [21, 22, 23]. In 2019 Google even announced that they reached quantum supremacy. They claimed that it would take their quantum processor Sycamore with 54 qubits (53 functional ones) about 200 seconds to sample one instance of a quantum circuit one million times, a task for which a state-of-the-art supercomputer would need around 10,000 years [21]. However, this claim turned out be be rather controversial, because IBM published on their research blog that the task could also be done in 2.5 days on a classical computer with a far greater fidelity [58]. Independent of whether quantum supremacy has already been reached or not, the whole discussion addresses a problem which is highly artificial and currently not relevant for real-world applications. To run more useful algorithms like Shor’s algorithm for prime factorization [53] or Grover’s algorithm for searching an unordered list [59], it is necessary to operate thousands or millions of qubits. To enable this, there is a multitude of challenges which still need to be overcome.

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Figure 1.2: Left: Mathematical representation of a qubit as Bloch sphere, which represents all possible states as superposition of \( \alpha \ket {0}+\beta \ket {1} \). Operations on a qubit are represented by unitary matrices, resulting in a rotation of the vector on the sphere. Right: Quantum computer from the IBM Q project. The golden chandelier in the photograph shows different stages, from the mK-stage at the bottom to room temperature at the top. Figure taken from [60].

One of the most important ones is the choice of the physical qubits. In theory, any two-state quantum system could be considered as a basis, however, no leading qubit technology has been established withing the QC community yet. Therefore, many different technologies are currently explored, for example trapped ion qubits [61], qubits based on crystal impurities [62, 63] or single photons [64]. The qubit-technologies used by the big tech-companies are superconducting qubits [21, 28] and silicon qubits [37, 23]. These technologies have been demonstrated already on small scales and they can be produced in industrial cleanrooms for 300mm wafers [65, 66, 67]. For these reasons, they are currently also in the focus of our research partner imec [67].

Superconducting Qubits

Among all qubit technologies, the superconducting qubit approach is currently the most advanced one in terms of the number of qubits, as can be seen in Fig. 1.1. Here, the qubits are based on Josephson Junctions (JJs), see Fig. 1.3 (a). Typically, JJs consist of two superconducting stripes, which are connected via a tunnel oxide in between. At deep-cryogenic temperatures (in the mK-regime) JJs act as non-linear inductors [68]. While a linear inductor in an LC-circuit would lead to equidistant energy levels in the corresponding quantum harmonic oscillator, the anharmonicity of a non-linear JJ leads to non-equidistant energy levels. This allows to take the ground state \( \ket {0} \) and the first excited state \( \ket {1} \) as two-state quantum system without allowing a higher state to become accessed. The manipulation of the qubit (which is the rotation on the Bloch sphere) can be induced by microwave pulses sent to an antenna which is coupled to the qubit. The frequency of this wave determines the rotation between the different energy levels. It has to be noted that there are various realizations of superconducting qubits based on non-linear inductors operating at cryogenic temperatures. A more detailed overview which realizations exist and how superconducting qubits work can be found in [68, 69, 70, 71].

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Figure 1.3: (a) Cross-section transmission electron microscope (TEM) of a fully patterned Josephson junction. (b) The scanning electron microscope (SEM) image of a Si electron spin qubit shows a single electron transistor (SET) for readout, two quantum dots (QDs) at the Si/SiO2  interface, and the 2-dimensional electron gas reservoir for loading the QDs. (c) The schematic of a silicon spin qubit shows multiple gates for the qubit confinement and two magnets for operating the qubits. Figures taken from  [72, 73, 67].

Electron Spin Qubits

Another class of qubits are silicon spin qubits, which is a collective name for various technologies, based upon using the spin of a charge carrier as two-state quantum system. There are various types of spin qubits, e.g. based on Si/SiGe [74], Si SOI [75], or based on Si MOS [76]. The latter ones are also in the focus of our research partner imec [67, 77, 73, 65] and are therefore discussed in more detail in the following. A SEM image of the qubit can be seen in Fig. 1.3 (b), where the single electron transistor (SET), the two quantum dots and the 2-dimensional electron gas (2-DEG) are highlighted. Several gates are needed to electrostatically confine the two quantum dots QD\( _1 \) and QD\( _2 \) located at the Si/SiO2 -interface as can be seen in Fig. 1.3 (c). The 2-DEG serves as a charge reservoir enabling the loading of the QDs. The qubits can then be manipulated with a magnetic field created by micromagnets via electric dipole spin resonance [78] (alternatively, electron spin resonance can be used). Using the SET it is possible to readout the spin states using spin-charge conversion [73, 79]. A series of qubit operations using the magnetic field allows then the execution of quantum algorithms. Unlike superconducting qubits, the fabrication of Si spin qubits could benefit from many advantages of modern CMOS scaling which makes the concept highly interesting for commercial applications [65]. In theory, silicon spin qubits are ideal candidates for a co-integration of CMOS control hardware and qubits on the same chip [76]. However, state of the art projects are dominated by superconducting qubits (see Fig. 1.1) while spin qubits lag behind. The main reason for this is the limiting gate fidelity which describes how close two realized quantum states are. The fidelity of spin qubits is below the threshold required for complex quantum algorithms which leads to error rates of gate operations around 1% and thus makes the up-scaling impossible [65]. One of the main limitations for fidelity is the non-uniformity of qubits, which arises from the fabrication process. Among other processes, interface defects between the Si and the SiO2  layer can be introduced during manufacturing, which has the consequence that every QD behaves slightly different and it is thus necessary to find for every qubit  the right operation voltage regime individually [80]. Here, knowledge from the semiconductor industry, specially from the field of device reliability, can be used to improve the interface quality and to further specify the limiting factors.

Classical Control Interface

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Figure 1.4: The first successful QCs use a dilution refrigerator for bringing the quantum processor to the sub-K regime. The qubits are controlled via coaxial cables with electronics at RT. Since this leads to a wiring bottleneck, lots of effort has been spent to design cryo-CMOS control interfaces working at the 4 K-stage [81]. Recently, first successes have been published bringing a monolithic co-integration of qubits and the cryo-CMOS control hardware to the cryogenic stage, where a large temperature gradient between the qubit layer at 50 mK and the control layer at 1 K to 3 K occurs [82, 83].

While the importance of the choice of the qubit technology is crucial, another less obvious bottle neck appears at the classical control interface for qubits. Until recently, existing QCs with a maximum of \( \sim \)100 qubits have used racks full of electronic equipment (RF sources, DC sources, etc.) at room-temperature, where each individual qubit is connected via several coaxial cables to electronic instruments [81]. For such small systems, fidelities of above 99% can already be reached [84, 85]. However, for QCs which should be able to solve real-world applications the operation of thousands or millions of physical qubits is necessary to perform calculations together with quantum-error correction schemes, such as surface codes [86, 87]. For such large-scale QCs the research approach of room-temperature electronics fails for multiple reasons. The signal integrity across the RF lines for controlling the qubits gets too low, the number of possible physical connections at the test chip is limited, and the damping by the high resistivity of the vacuum throughputs becomes too high. Therefore, the classical control interface must be integrated within the cryostat and located as close as possible to the quantum processor. For this, CMOS technology is an ideal candidate for the control interface, because it can be produced in a high-quality commercially, allows the integration of billions of transistors, has a low power consumption and is functional even in the sub-Kelvin regime [88, 89, 90, 91, 92]. However, to avoid heat transfer to the qubits, the power budget of the control interface is extremely limited to approximately 1 W at the 4-K stage and to less than 10 µW at the mK stage [93, 89]. Additionally, noise leads to decoherence which reduces the qubit fidelity [78]. With these given restrictions near-quantum-limit amplifiers [94, 95, 96], ultralow-loss resonators [97, 98], circulators [99], multiplexers [100], cryogenic filters [101], wirebonds [102], DAC/ADCs [103, 104, 105], and many more components have been developed to realize cryogenic circuits. These building blocks have recently enabled the design of fully-fledged cryo-CMOS controllers for qubits, located at the 4-K stage [81, 92, 106]. This is an important intermediate step which not only allows to drastically reduce wiring but is also an important step towards fully integrated control electronics and qubits enabling up-scaling, as can be seen in Fig. 1.4. Recently, a first proof-of-concept of a monolithically integrated quantum–classical hybrid circuit was realized [83, 82]. This approach of unifying spin qubits  in Si quantum dots and CMOS circuit technology could have the potential of using very large-scale integration (VLSI) and the experience collected over decades in the semiconductor industry for the production of monolithical qubits.

1.2.2 High Performance Computing

Another potential application for cryo-CMOS application-specific integrated circuits (ASICs) is the field of high performance computing. The changes in the (math image)((math image)) characteristics of the transistors which are the core of the ASICs towards cryogenic temperatures, can be deliberately used to increase logic switching speed or to decrease the supply voltage \( V_\mathrm {DD} \), which allows a reduction of the total energy consumption [15, 16, 17]. Fig. 1.5 shows qualitatively how the (math image)((math image)) curve of a MOSFET changes between room temperature and 4.2 K. At cryogenic temperatures, phonon scattering becomes reduced which leads to a higher charge carrier mobility, and as a consequence to an increasing on-state current (math image). Also the subthreshold slope gets steeper leading to an increasing transconductance (math image). Additionally, the threshold voltage (math image) increases due to the shifting semiconductor Fermi level and the temperature dependent band gap widening. A detailed discussion of these properties including certain saturation effects is given in Section 6.


Figure 1.5: The temperature dependence of the charge carrier mobility, the Fermi level, the band gap widening and other MOSFET parameters affects the (math image)((math image)) transition curve. Towards cryogenic temperatures the (math image)((math image)) curve gets steeper and the on-state current increases. This can be used in combination with threshold voltage (math image) scaling to decrease the supply voltage \( V_\mathrm {DD} \) which allows to increase the logic switching rate and to reduce total power consumption [15].

While at room temperature \( V_\mathrm {DD} \) can not be scaled down due to the constraining (math image) and a large \( SS \) which would result in a significant off-state current, the steep transition at cryogenic temperatures opens new possibilities. For instance, a scaling of (math image) allows an operation at considerably lower \( V_\mathrm {DD} \), as indicated in Fig. 1.5 [16]. There are multiple approaches for achieving the (math image) scaling, e.g. it is possible to optimize the gate metal by choosing a metal with a band edge work function which meets (math image) at the reduced target [15]. Additionally, lower band gap channel materials such as SiGe or Ge can be used to reduce (math image) [15]. Another approach aims for using metal-oxide cap induced interfacial dipole layers [15] to optimize (math image). Overall, a device with an optimized (math image) operating at cryogenic temperatures allowing a low-\( V_\mathrm {DD} \) operation has the potential of a significant higher logic switching rate. Chiang et al. proposed for an advanced FinFET technology a speed increase of around 50% when operating at 77 K with a constant operating power [15]. For a planar 28 nm high-κ metal gate technology, Saligram et al. claimed a 90% performance/Watt improvement while operating at 6 K, however, in their calculation the cost of cooling has not been included [107]. But even with including the power of the needed refrigeration, a net power reduction of approximately 30% can be achieved [15].

Next to (math image) scaling, the operation of MOSFETs at a very low-\( V_\mathrm {DD} \) leads to additional reliability challenges which have to be considered for circuit design for cryo-CMOS applications. With the lowering of (math image) the margins for (math image) and \( SS \) also become more narrow meaning that the variability in the transfer curve must be minimized to guarantee a reliable logical switching. Furthermore, reliability issues such as bias temperature instability (BTI) and random telegraph noise (RTN), which are introduced in the upcoming section, must be reduced to a minimum, because low-\( V_\mathrm {DD} \) applications do not leave room for large threshold voltage shifts [108].