Phenomenological Single-Particle
Modeling of Reactive Transport
in Semiconductor Processing
5.3 Reactor Loading Effect
As already seen in Tab. 5.2, there appears to be a reduction in the
In principle, reactor loading can be modeled if the total exposed wafer area is known [46]. However, this information is not always accessible, and, additionally, such models still require fitting coefficients. Instead, the approach taken is to treat the PWRs, thus the loading effect, as a model parameter not only for each reactor condition but also for each photoresist or hardmask configuration. At the core of this approach is the approximation that the exposed area is constant during the etch step which is valid for low photoresist or hardmask etch rates.
This effect has been experimentally investigated by Panduranga et al. [171]. In their work, they attempt to deliberately construct a regime with lower etch rates by placing the individual chips over a larger and
unmasked silicon carrier wafer.
They investigate two distinct situations: A low loading regime, by placing the chips directly over the stainless steel carrier plate, and a high loading regime with chips on the silicon carrier wafer. To quantify the etch depth, the
chips are initially patterned with a hardmask (chromium-on-oxide) containing cylindrical holes with
The original authors assume that there are no limitations due to visibility, thus they calculate the PWRs from the etch depths at the center. However, since visibility effects often play a subtle role, the simulation considers
the entire geometry. The