« PreviousUpNext »Contents
Previous: 14 MOSFET Characterization Array    Top: 14 MOSFET Characterization Array    Next: 14.3 Results 2

14.2 Experimental Setup 2

The experimental setup used to probe the devices is shown in Figure 14.4.

(-tikz- diagram)

Figure 14.4:  The transistor array is entirely controlled by the TMI with digital and analog signals electrically isolated. To allow temperature accelerated tests, the structure is mounted onto a heater together with a temperature sensor controlled by an external hardware. Both controllers and the measurements are monitored by the jobserver, see Section 9.3.

Note that the reliability characterization array is entirely controlled by the TMI. Therefore the TMI is configured with two VUs, providing six analog voltages for \( \VD   \), \( \VG   \), \( \VS   \) and \( \VB   \) share a common output, \( \VDoff   \), \( \VGPoff   \), and \( \VGNoff   \). The drain-source current is monitored using a modified version of the DCU. As the array requires a user selectable, non-zero source potential, the SCU has to be used for drain-source monitoring. In this context, it is worth to note that the TMI is able to provide the six analog voltages, and thus replaces three general purpose Keithley instruments. Thereby the total costs of the setup are reduced by a factor of around 15–20.

Another very important issue is the reduction of the noise level, especially for high-precision, low current, measurements. For this purpose, the analog and digital power supply, as well as all signal lines, are electrically isolated. Furthermore, the temperature is a crucial parameter in all experiments. For instance, the charge capture and emission transitions caused by single defects are very sensitive to the device temperature. Thus the test chip is mounted onto an external heater which allows to apply defined temperatures in the range of \( \SI {25}{\celsius } \) up to \( \SI {150}{\celsius } \). In addition, defined temperature profiles can be applied similar to polyheater device structures [135].

To study the detrimental impact of NBTI and PBTI at the same technology, the test array contains n-channel and p-channel devices. The entire chip is designed to operate at \( \VDD =\SI {1.8}{\volt } \). Although the break-down voltage of the gate stacks is much higher, a stress voltage exceeding \( \VDD    \) will damage to the transmission gates. Hence, the voltages at the terminals must not exceed \( \VDD   \), however, negative voltages are necessary to characterize pMOSFETs. This requires different source potentials depending whether a n-channel or a p-channel MOSFET is measured. The corresponding voltages applied at the terminals and the resulting voltage ranges are summarized in Table 14.2 and Table 14.3.

Table 14.2:  The optimized values for the terminal voltages of the array structure are summarized for pMOSFETs and nMOSFETs.

(math image) (math image) (math image) (math image)
nMOSFET \( \SI {0.15}{\volt } \) \( \SI {0.15}{\volt } \) \( \SI {0.3}{\volt } \) \( \SI {0}{\volt } \)
pMOSFET \( \SI {1.65}{\volt } \) \( \SI {1.65}{\volt } \) \( \SI {1.8}{\volt } \) \( \SI {1.5}{\volt } \)

Table 14.3:  The available voltage ranges for the transistor array are calculated using the values from Table 14.2 considering a nominal \( \VDD =\SI {1.8}{\volt } \).

(math image) (math image) (math image) (math image)
nMOSFET \( \SI {-0.15}{\volt } \) to \( \SI {1.65}{\volt } \) \( \SI {-0.15}{\volt } \) to \( \SI {1.65}{\volt } \) \( \SI {0.15}{\volt } \) \( \SI {-0.15}{\volt } \)
pMOSFET \( \SI {-1.65}{\volt } \) to \( \SI {0.15}{\volt } \) \( \SI {-1.65}{\volt } \) to \( \SI {0.15}{\volt } \) \( \SI {0.15}{\volt } \) \( \SI {-0.15}{\volt } \)

It is notable that using the deliberate set of biases from Table 14.2 a significant reduction of the leakage current is measured, see Figure 14.5.


Figure 14.5:  A typical (math image) characteristics recorded for a nMOSFET from the test array using the TMI. By using optimized values for the terminal voltages, see Table 14.2, a significantly reduced leakage current is measured.

Furthermore, the effective gate bias range to study charge trapping is extended especially around the threshold voltage.

« PreviousUpNext »Contents
Previous: 14 MOSFET Characterization Array    Top: 14 MOSFET Characterization Array    Next: 14.3 Results 2