The big advantage of such a test structure is the easy and reliable device selection. For instance, any contact issue as typically occur when a probe station is used can be avoided. In addition, due to thermal expansions, the probes usually have to be realigned during and after temperature changes. Although the latter can be overcome by using devices mounted into ceramic packages, the number of directly accessible devices still remains very small. Both issues can be addressed using characterization arrays.
So far, the TDDS has been used to extract the CCDF of step heights from pMOSFET with , see Figure 14.6.
As can be seen, the step heights are bimodally distributed in agreement with previous investigations [165, MWJ1].
It has to be noted that the experimental setup using the MOSFET array structure is still under development, thus only few results are available yet. However, major advances in understanding the charge trapping kinetics in high-k technology and device variability are expected from this considerable extended database.« PreviousUpNext »Contents