As apparently BTI is still not fully understood, the definition of a generalized experimental setup to quantify the BTI induced deviation of the device characteristics from its nominal behavior remains difficult. To measure the impact of charge trapping on the device performance, shifts of the threshold voltage and changes in the subthreshold-slope of the transistors or changes of the characteristics are typically investigated. For this, several techniques have been proposed. The developed setups are mostly based on programmable general purpose instruments extended with partly custom-made circuits and configurations to compensate for missing features and circumvent various limitations. In the following sections the methods which have been used to study BTI in various technology nodes are briefly summarized
One method to study the threshold voltage shift relies on measuring the characteristics prior and after the device has been stressed. The threshold voltage shift is then calculated as the difference between the gate voltages necessary to achieve the same drain-source current for both characteristics. For instance, the voltage level corresponding to the maximum of the device transconductance, that is , can be used as gate voltage at which the threshold voltage shift is determined [68, 69]. The advantage of this method is that it can be easily implemented using general purpose instruments. However, the recovery of the device during slow sweeps leads to an underestimation of the threshold voltage shift. Furthermore, the choice sweep range is crucial as during such slow voltage sweeps the device may see some stress, particularly for the initial measured on a fresh device. Conversely, a ramps starting from accumulation accelerates de-trapping of the trapped charge, and will thereby lead to an underestimation of threshold voltage shift too.
To measure fast sweeps, the pulse method was proposed in  and further optimized in [71, 72]. It allows to measure complete characteristics within , see Figure 4.14.
Using the fast pulse technique threshold voltage shift is reported to be about times and about times larger for pMOSFETs and nMOSFETs, respectively, compared to data extracted from conventionally slow measured DC sweeps .
Based on the pulse technique an ultra-fast method has been presented [ANG11, 73], see Figure 4.15.
The setup has been realized using Keithley 4200 semiconductor characterization instruments providing the required SMUs and pulse generators. With this technique measurement pulses in the sub regime are achieved resulting in a minimized recovery of the device during these pulses.
Although the presented methods allow to characterize BTI, their applicability is limited to large-area devices. This limitation is a consequence of the large current measurement resolution around . To properly resolve currents typical in nanoscale transistors a current resolution at least in the sub-nanoampere regime is required.
Quite recently, the ultra fast single-pulse method, which employs the split technique to determine the channel mobility, was presented . Usually, the mobility degradation measurement technique relies on measuring the channel conduction current and a subsequent characteristics. The effective channel mobility can then be calculated using the relation [75, 76, 77, 78, 79]
with extracted from the measurement. Note that the split technique sets the drain bias to during measurements and during the sweep which is necessary to determine . To account for any impact of on the channel mobility and to avoid any rearrangement of the connectors and cables when the measurement configuration is changed to the configuration, the ultra fast single-pulse (UFSP) method has been proposed , see Figure 4.16.
To monitor the transient characteristics of the threshold voltage shift the so called on-the-fly (OTF) method was introduced in . To eliminate any recovery-related effects, the stress signal is not interrupted during measurement. In the OTF technique the drain current is typically recorded in the linear regime, that is , and measured using periodic pulses around the gate bias, see Figure 4.17 (left).
Using the measured the threshold voltage shift can be calculated to 
with the estimated transconductance
Nevertheless, as the measurement delay of general purpose SMUs is pretty large, in  an additional current-to-voltage converter connected to a DSO is used to monitor the fast recovery by measuring the current through the device at the source terminal of the transistor, see Figure 4.17. Both the SMU and the DSO are synchronized with the pulse generatorunit (PGU) providing the gate bias. By using this configuration a fast measurement delay of around is achieved.
To perform measure-stress-measure (MSM) experiments the combination of a PCI interface card providing several analog to digital converters (ADCs) and digital to analog converters (DACs), and custom-made current-to-voltage converters were used in [83, 84], see Figure 4.18.
As the setup is designed to investigate several devices simultaneously, the PCI interface requires synchronized DACs to provide the stress and recovery biases and synchronized ADCs to record the output voltage of the current-to-voltage converters. Using this setup controlled stress and recovery cycles with a minimum delay of can be achieved.
The so called fastVT method proposed by [85, 86] is a very elaborate technique which allows to directly monitor the threshold voltage shift. The operating principle is shown in Figure 4.19.
During the stress cycle the switches are put into position ’s’, thereby disabling the OPAMP circuit and setting the terminals of the device under test (DUT) to whereas . The recovery conditions are provided by setting the switches to position ’m’. In that case the drain voltage changes to and the feedback loop built around the OPAMP is closed. The recovery gate bias is now controlled by the OPAMP to minimize the current difference between the drain-source current through the device and the reference current given by . To monitor the threshold voltage shift a combination of a slow sampling unit to record the data for and a high speed DSO to record the data within is used. The advantage of this method is that data can be directly monitored after the feedback loop setup time, which is typically about 0.5 µs.
So far the fastVT method was successfully used to monitor single charge trapping in nanoscale transistors [87, 88, 89].
Common to all these different measurement methods is the observation that high speed measurements with sampling times around can not be achieved with general purpose instruments. Most of the setups are configured using synchronized combinations of conventional SMUs and pulse generators to provide output voltages and DSOs and SMUs to record the currents. To achieve high measurement accuracy, additional custom-made hardware is typically required. However, the handling of such setups is inconvenient and error-prone but necessary as there is no suitable general-purpose measurement setup available commercially.
In our initial efforts to study charge trapping in nanoscale devices we performed stress and measure experiments using general purpose SMUs. However, it turned out that the measurement delay was too large () and the threshold voltage shift resolution too low to resolve threshold voltage shifts below . To overcome both limitations we developed our own measurement setup, called time-dependent defect spectroscopy measurement instrument (TMI). In this context the time-dependent defect spectroscopy (TDDS) refers to the measurement technique proposed to study charge trapping in nanoscale devices, and will be discussed in great detail in Section 8.
Although the main focus during development of the TMI was the study of charge trapping in nanoscale devices, the TMI was also successfully used for the characterization of large-area transistors, and was quite recently used to investigate alternative structures such as Galiumnitride (GaN) high-electron-mobility transistors (HEMTs). A practical side effect of the TMI are the low production costs compared to general purpose instruments and the possibility to modify the configuration individually. For instance, the TMI has been recently configured to control and measure transistor array structures, see Section 14. In this application the TMI replaces three Keithleys and thereby reduces the setup costs by a factor of around 15–20. Furthermore, on the one hand BTI often requires very time-consuming measurements and on the other hand the achieved results have to be confirmed by investigating several identical devices. To achieve this within a reasonable time span, parallization of measurements is required. Due to the manageable costs of the TMI and the flexible adjustment to any setup, the TMI has proven invaluable for the rigorous study of BTI.
In the first part of this thesis, the most important features of BTI are summarized, followed by an introduction of defect modeling. A particular focus will be put onto the four-state NMP model which has by now been successfully used to explain charge trapping on a wide range of technologies. Next, the TDDS is introduced and the design concept and features of the TMI are discussed in greater detail. Then another important aspect, namely the analysis of the collected measurement data is presented. The latter requires elaborate algorithms to analyze equidistant and non-equidistant sampled measurement data. Furthermore, as the contributions of single traps to the total threshold voltage shift can be very small, the separation of capture/emission events from measurement noise requires careful attention. Also the observation of volatile defects, defects producing multiple emission events, and random telegraph noise (RTN) signals have to be studied individually. Finally, recent findings concerning NBTI and PBTI in MOSFETs and PBTI in strained SiGe devices are presented.« PreviousUpNext »Contents