« PreviousUpNext »Contents

Previous: 7 Modeling of Bias Temperature Instabilities Top: 7 Modeling of Bias Temperature Instabilities Next: 7.3 Recoverable Component of Bias Temperature Instabilities

In contrast to large-area devices the recovery of the threshold voltage shift recorded from nanoscale devices proceeds in discrete steps, see Section ?? and Figure ??. To describe such a recovery behavior a stochastic charge trapping model is required rather than an approximation by a simple power law, because the latter can not capture the discrete recovery of nanoscale transistors, see Section 6. In such datasets each single defect can be clearly identified by its capture time , emission time and its step height, and can either be neutral or charged depending on whether a low or high gate bias is applied. In previous studies, single charge trapping has been studied from RTN signals recorded on small-area devices [104]. During these investigations the charge capture and emission times have been found to be very sensitive to the applied bias. This bias dependence of the charge capture and charge emission is also observed when stress/recovery experiments are performed and analyzed. In contrast to traditional RTN analysis, stress/recovery experiments rely on charging and discharging a single defect during the stress and recovery phases, respectively. In such experiments a high gate bias is initially applied to charge the defect. Next, the gate voltage is switched to the recovery bias and the drain-source current is recorded. From the experimental data the capture and emission time of single defects can now be extracted, see Section 8. Hence the charge capture and emission time is very sensitive to the applied bias and different biases are used during stress and recovery, each charge state can be described by its characteristic capture and emission times and or and , respectively. Considering a two stage model [89] the transition times between the neutral and charged state can then be expressed as

and

for charge capture and charge emission, respectively. The occupancies, i.e. the probability that the defects is either charged after the stress bias has been applied or the defect is neutral after the recovery bias has been applied for and indefinitely long time, are given by

The stress time dependent transition for the capture process reads

and the time dependent occupancy, i.e. the probability of a defect to be charged after the stress time and recovery time has elapsed, becomes

considering that the defect can switch back to its neutral state after elapsed and the low bias is applied at the gate. To simplify the equations stated above we can assume that each defect emits his charge after indefinitely long recovery time which means that the low level occupancy can be considered zero. This yields

with a prefactor which represents the capture probability for . At a first glance, one might expect this prefactor to be close to 1 but this is only the case for very large gate biases. As soon as the stress voltage is reduced, the capture time increases while the emission time decreases, thereby resulting in . This means that although a nominal stress bias is applied the defect can emit its charge during stress and thus is never occupied with a probability of . Nonetheless, using the occupancy functions the normalized transition function can be defined

and is shown in Figure 7.2 for different capture and emission times.

The total threshold voltage shift can finally be expressed by

with the contribution of defect to the and the occupancy [89]. Using (7.19) the threshold voltage shift due to charge trapping is expressed in terms of charge transitions caused by single defects. As already mentioned, in nanoscale devices only a handful of defects are present. Furthermore, the impact of these defects on the total is can be resolved by our measurement equipment and the single charge transitions manifest as discrete steps in the drain-source current. By studying the dependence of the on the gate area it has been found that the trap density and the average step height follow and , respectively. As a consequence, in large-area devices can also be expressed in terms of single charge trapping using (7.19), however, larger trap densities with smaller contributions to the total have to be considered. Note that, because is typically below the measurement resolution single charge trapping can only be investigated in modern nanoscale transistors.

The first modeling attempts trying to describe charge trapping were based on the assumption that charge capture and charge emission can be described by elastic tunneling processes [105, 106, 107], see Figure 7.3.

During an elastic tunneling process the carrier does not change its energy which is illustrated by the same energy level of the defect in the dielectrics and the carrier located in the valence/conduction band. The charge transfer transitions considered as elastic tunneling processes lead to charge transition times which are proportional to the trap depth [109]

This dependency introduces some difficulties when describing charge trapping. In order to correctly reproduce the recovery behavior of large-area transistors, widely distributed charge emission times are required. However, such a broad distribution can only be achieved by devices having thick oxides, which is not the case in modern ultra-scaled devices [110]. Furthermore, elastic tunneling is inherently temperature independent and can not explain the strong temperature acceleration of charge capture and emission, which becomes visible when single defects are studied, see Section 6.1. As a consequence, models based on elastic tunneling can not provide an accurate description of charge trapping in the context of BTI.

The most promising model to describe BTI was initially proposed in [109] and refined in [111, 87, 112]. It employs the concept of charge trapping which was introduced to describe RTN signals and noise [113, 114] and relies on hole trapping in defect sites located in the oxide supported by a multiphonen emission (MPE) process [115, 116]. Compared to elastic tunneling considerably larger capture and emission times are achieved for MPE processes [117].

Initially, to explain charge trapping of single defects the HDL model for a switching oxide trap was used [118]. The HDL model is two stage model, and has been proven to explain the characteristics during stress and recovery [109], see Figure 7.4.

In this model a neutral defect (state 1) can capture a hole and afterwards relax into the positively charge E’ center configuration (state 2). From its charged state, the defect can either be repeatedly uncharged and charged (state 3), or the defect can be uncharged and subsequently recover into its neutral state. Both pathways describe defects which contribute to the recoverable . Alternatively, starting from state 2 the defect can be passivated by a hydrogen released from an interface state (state 4) and contribute to the permanent . In this model, the transition between state 1 and state 2 is modeled using the multiphonon-field-assisted tunneling (MPFAT) mechanism [119, 120] and the transition between state 2 and state 4 is described by field dependent thermal barriers, also know as double-well model [121], see Section 7.4.1. By using this switching trap model the strong bias dependence of the charge capture and emission time of single defects as well as their temperature dependence can be explained [122].

To study the complex bias and temperature dependence of charge capture and charge emission transitions of single defects, the TDDS has been proposed, see Section 8. Detailed TDDS studies have revealed defects with strongly bias-dependent emission times, an observation which can be partly described by the two-stage switching trap model. Additionally, a notable number of single defects show bias-independent emission times. To model this particular bias-independency the HDL model is extended by an additional metastable state [122, 123, 112] leading to the four-state NMP model.

« PreviousUpNext »ContentsPrevious: 7 Modeling of Bias Temperature Instabilities Top: 7 Modeling of Bias Temperature Instabilities Next: 7.3 Recoverable Component of Bias Temperature Instabilities