MOSFETs have a large number of traps with detrimental impact on their device performance. In order to explore the mechanism responsible for altering of the device characteristics, 1/f noise and random telegraph signal (RTS)  have been studied in large-area and nanoscale transistors. RTS, also known as random telegraph noise, have been recorded and analyzed to study the capture and emission time of single defects. Therefore charge capture and charge emission processes have to appear within the experimental window with measurable time resolution. As the charge transfer transition times are very sensitive to the gate bias, RTS analysis only provides information on the charge trapping kinetics within a very narrow gate bias range.
A standardized method to detect a broad variety of traps in semiconductors is the deep level transient spectroscopy (DLTS) . The DLTS relies on the measurement of the capacitance of p-n junctions and works as follows: Initially, a reversed bias is applied to a p/n junction, thus a depletion region is formed at the interface. By applying a short voltage pulse () at the forward biased p/n junction, the depletion layer shrinks and traps which are energetically aligned below the shifted Fermi-level become charged. When the applied bias is switched back the newly charged trap does not immediately become neutralized, resulting in a wider depletion layer. The increase of the depletion layer width leads to a measurable decrease of the junction capacitance.
The TDDS applies DLTS to small devices and augments it by a statistical analysis. The only prerequisite is that the devices have to be small enough to exhibit measurable discrete capture and emission events. An overview of the estimated mean step heights for different technologies based can be seen in Figure 8.1.
Quite remarkable, in most recent technology nodes less than one trap per device on average is present. However, as the number of traps dramatically decreases with the device geometry, their impact gets worse. For instance, the average of a single defect the present in a transistor produced within the exceeds . Note that is the typically criteria used for lifetime projections. Thus the proper operation of a single device can be solely determined by only one defect.
In all our single defect investigations the step heights are widely distributed from several hundred millivolt up to and even higher depending on the device geometry. Furthermore, in many cases the distribution can be well approximated by an exponential distribution. The smallest detectable step heights are a consequence of the limited current measurement resolution and the device geometry. As the average step height becomes smaller with increasing channel area the number of defects producing experimentally resolvable shifts decreases and are visible as measurement noise thereby obscuring the recovery traces. The detectable step heights using the TMI at the best current resolution are around and for SiON nMOSFETs and high-k MOSFETs, respectively, see Chapter 11 and Chapter 12.
In most cases single defects can be unambiguously identified by their capture and emission time as well as their step heights. The capture times themselves depend on the gate bias and on the device temperature. Although the emission times are temperature dependent too, they have been observed to be either bias independent, so called fixed traps or bias dependent, so called switching traps, shown in Figure 8.2 and Figure 8.3, respectively.
The previously introduced four-state NMP model has been developed to explain the bias and temperature dependence of these defects. From the simulations the location of the trap inside the oxide and its energy level can be estimated. As the four-state NMP requires several parameters which describe complex dependencies of the model itself, detailed knowledge of the charge transition times over a wide gate voltage range are required. Therefore DC stress, pulse stress and AC stress signals are used within the framework of TDDS to achieve meaningful trapping time characteristics for single defects.
When a nanoscale device is subjected to BTI stress, a defect can become charged if its (i) a capture time is smaller than the stress time and (ii) if it is energetically realigned below or above the Fermi-level for the applied stress bias in case of a pMOSFET or nMOSFET, respectively. When a recovery bias is applied at the gate contact, the trap level is shifted above/below the Fermi-level and the defect can become uncharged. The charge emission event of several defects is visible in the recovery traces in Figure 8.4. Also visible is a defect producing RTN which is characterized by subsequent charge capture and emission events.
Next, the measured recovery traces have to be analyzed for discrete shifts in . For this a sophisticated step detection algorithm is used, which is described in detail in Chapter 10. The extracted emission events occurring at with step height are then collected in the emission time versus step height plane, called spectral map. Therein each single charge emission event is marked, see Figure 8.5.
By collecting all charge emission events from repeatedly measured recovery traces recorded at the same bias conditions, stress/recovery time, and device temperature the emission events form clusters in the spectral map. Each cluster delivers information about the defect step height and emission time. The latter can be calculated as the average of all single emission events contributing to a certain cluster by
with the number of emission events. In the spectral map shown in Figure 8.6 based on the measurement data recorded using a pMOSFETs with a geometry of and .
As can be seen, six defects with various step heights and widely distributed emission times are are visible.
As previously shown, the average emission time is calculated from typically 100 recovery traces, each measured under the same experimental conditions. In contrast, the charge capture time can not be determined directly. To extract the capture time DC stress/measurement sequences with increasing stress times are used. During the stress phases a constant stress bias is applied at the gate for a certain stress time . Under these circumstances, the expectation value of the occupancy, which is the probability of a defect to become charged during stress, follows
with the equilibrium occupancy observed after indefinitely long stress. When switching to recovery bias conditions the defect become discharged and the occupancy functions then reads
The correlation between different stress times and the occupancy function is shown in Figure 8.7.
Obviously, the longer the device is stressed the more likely the defect becomes charged. Given that the used recovery gate bias and recovery time guarantee , the defect will very likely emit its charge during recovery, presuming the defect has been charged during stress. Thus by repeatedly stressing the device and recording the device recovery, the number of charge capture transitions during stress equals the number of emission events during recovery. Using (8.2), the capture time can be extracted by analyzing typically 100 traces at different stress times, see Figure 8.8.
By applying the DC measurement method the bias dependence of the emission time can only be studied in a very narrow gate voltage range. For pMOSFETs, for leads to a large drain-source current during device recovery. As the measurement resolution decreases towards higher current ranges of the measurement unit, the value for the smallest measurable step heights increase. Towards the drain-source current becomes very small close to the measurement resolution, see Figure 8.9.
To circumvent this limitation the DC stress signal is extended by an additional accumulation voltage pulse , see Figure 8.10.
The modified occupancy function then becomes
with the voltage pulse width.
The idea behind the additional voltage pulse is very simple. Under the assumption that, the stress time and the stress voltage of the conventional DC stress cycle lead to , implying the defect has been charged, the accumulation voltage pulse can discharge the defect. If this is the case, this defect will not contribute to the subsequent recovery trace. Conversely, if the defect is not discharged during the accumulation pulse, the charge emission will occur during relaxation and the corresponding step will be visible in the recovery trace. As charge emission is a stochastic process, the probability of the defect to emit during recovery strongly depends on the choice of and . By repeatedly performing the experiment using the same biases and times, the probability of the defect to emit its charge during can be extracted by counting the number of emission events during subsequent device recovery. Analogously to the charge capture events, the dependence of the number of emission events on the voltage pulse width can be described by an exponential function
An example for the extraction of the emission time using an additional accumulation voltage pulse during stress is shown in Figure 8.11.
The impact of the voltage pulse on the defect occupancy for the defects B1 and B3 is shown in Figure 8.12 and Figure 8.13, respectively. For the fixed trap B1 the occupancy is not affected by , thus a bias independent emission time characteristic is obtained. For defect B3, the exponential occupancy characteristic is shifted towards shorter times for an increased voltage pulse.
To considerably extend the gate bias range for the extraction of the charge capture emission time a voltage pulse, that is the dynamic TDDS, between the DC stress and recovery period is introduced, see Figure 8.14.
As previously mentioned, the capture time can not be extracted directly from the recovery traces. Therefore, a similar measurement scheme has to be applied as for the extraction of the emission time using pulse measurements.
As long as the recovery traces only show emission events which have significantly different step heights and disjunct emission times, the identification of the single defects is straightforward. However, this case is not always guaranteed, and thus fully automatic device characterization is very challenging. The evaluation of TDDS data requires considerable care. In order to demonstrate some difficulties during cluster detection and further analysis, assume two defects with their emission times very close to each other, but with different step heights, see Figure 8.15.
Again, the tuple extracted from the recovery traces form two clusters around the corresponding mean step heights and emission times. Nevertheless, when these two traps emit within the same data sampling interval, a large cumulative shift occurs. As a consequence, a third cluster in the spectral map is visible. The step height of this cluster equals the sum of the two initial traps, and is arranged around the overlap of the initial clusters. Thus this coincidence that both defects emit at the same time leads to a reduced occupancy. This can lead to slightly shifted emission times. This concern has also be addressed when calculating the charge capture time. The extraction of relies on counting the emission events at different stress times. Following from that, the calculated capture time is distorted which in turn leads to an error of the parameterset extracted by the four-state NMP model.« PreviousUpNext »Contents