With the aggressive scaling of the device dimensions, reliability challenges such as bias temperature instabilities (BTI), hot carrier degradation (HCD) or stress induced leackage current (SILC) have become more severe. The two former are due to charging and discharging of oxide defects and interface states as well as the creation of new defects. Newly created defects inside the oxide can act as trap assisted tunneling (TAT) centers, thereby increasing the tunneling current through the oxide after device stress. This phenomenon is known as SILC and can cause some difficulties in thin oxides in the context of static random access memory (SRAM) devices [45, 46]. In the worst case only one defect is required to form a tunneling path for electrons from the gate to the channel. This implies that SRAM cells will become unintentionally discharged if the oxides are too thin.
Back in the 1960s Miura et al. observed an increase of the electron concentration at flat band bias conditions after a MOS structure had been subjected to a positive bias stress. They linked their observation to the presence of vacancies located in the oxide . After this first observation little attention had been paid to this phenomenon for more than 30 years until the introduction of nitrogen into the gate stack to suppress boron outdiffusion, which in turn led to a dramatic increase of this instability. Today this phenomena is well known as the bias temperature instabilities (BTI), and has attracted the interest of the semiconductor industry and researchers alike. As a consequence, a vast amount of literature is available on this topic, which, however, contains numerous contradictory claims, thereby making BTI a highly controversial issue.
The detrimental impact of BTI on the device performance is typically expressed by a shift in the threshold voltage and a degradation of the channel mobility. To a certain extent the performance of both, nMOSFETs and pMOSFETs, is seriously affected by BTI. In this context, the terms positive bias temperature instabilities (PBTI) and NBTI are commonly used and thereby refer to the positive or negative gate bias used in enhancement-mode devices during stress. Regardless of whether the MOSFET is subjected to PBTI or NBTI stress, the defects charged during stress can become uncharged during recovery and thus the device partially recovers on very large time scales. The contribution of each single defect to the total threshold voltage shift therein strongly depends on the device geometry. In large-area devices numerous defects are present, however, their average contribution to the threshold voltage shift is very small, see Figure 4.9 (left), and can not resolved by measurements. Thus a continuous recovery behavior is observed.
In nanoscale devices the situation is completely different. Due to the reduction of the device width and length below a few hundred nanometers and the thinning of the gate insulator to approximately only a handful of defects exist in these devices, see Figure 4.9 (right). In contrast to their large area counterparts, the contribution of each particular defect, i.e. the charge capture and charge emission processes, can now be resolved by measurements and are visible as discrete steps in the drain-source current. Thus the charge trapping kinetics of single defects can be studied in detail, as it is done within the framework of the time-dependent defect spectroscopy (TDDS), see Section 8.
Furthermore, the impact of BTI strongly depends on the device technology. In the case of conventional oxides, NBTI in p-channel MOSFETs is much more pronounced compared to PBTI on nMOSFETs. Since nitrogen was introduced to fabricate oxides, BTI has became a more severe reliability issue and is observed in both nMOSFETs and pMOSFETs. In high-k gate stacks both phenomena, PBTI and NBTI, play an important role and are currently investigated intensively.
Another important device reliability issue is the degradation of the devices due to hot carriers, known as hot carrier degradation (HCD). In this context the term hot refers to the high energy of carriers which are accelerated by the electric field. Such hot carriers can damage the /Si interface by dissociating neutral Si-H bonds and leaving electrically active dangling Si-H bond behind, see Figure 4.10.
There are four main modes of hot carrier stress :
(i) Channel Hot Electron (CHE) Stress: Electrons with energies above a certain threshold are able to trigger a bond dissociation mechanism, which is referred to as single particle (SP) mechanism. This SP mechanism is dominant in large-area devices. However, in nanoscale transistors these carriers do not have sufficient energy to directly create a dangling bond. In such devices the carriers induce a dissociation of the bond by a series of collisions of lower energetical carriers, which is associated with the so called multiple particle process . CHE stress is the most important regime in modern scaled MOSFETs.
(ii) Substrate Hot Electron (SHE) Stress: High bulk voltages cause a large electric field in the substrate which can accelerate carriers from the p-n junction located below the conducting channel towards the insulator interface. Again, if the energy of the carriers is high enough they are injected into the oxide.
(iii) Drain Avalanche Hot Carrier (DAHC) Stress: The channel pinch-off near the drain leads to a high vertical field in this area. The electrons and holes generated by impact ionization can be either injected into the oxide or contribute to a substrate current.
(iv) Secondarily Generated Hot Electron (SGHC) Stress: The SGHC injection originates from impact ionization of carriers generated due to DAHC and are accelerated towards the bulk.
Considering the experimental conditions, the difference between BTI stress and HCD stress is that the former uses whereas during HCD stress or depending on the channel length is typically used [50, 48]. Furthermore, the impact of HCD is twofold. The interface states generated during stress can capture carriers, become charged and perturb the device electrostatics which leads to a threshold voltage change. Charged defects can also degrade the carrier mobility and hence the drain current.
The initial investigations on HCD where carried out on long channel devices  operating at high drain-source voltages. However, in modern nanoscale transistors lower operating voltages are typically used. Nonetheless, even if hot electrons are unlikely in such nanoscale devices a degradation of device performance due to HCD is observed [52, 53]. As a consequence, the picture of HCD has to be extended to consider the contribution of cold carriers [54, 55, 56]. In contrast to hot carriers which can directly create an interface state, the dissociation of the Si-H bond involving cold carriers is stimulated by a series of particles, based on the principle of multiple vibrational excitation .
Recent reliability studies in ultra-scaled FinFETs  have shown that in these devices BTI still remains a challenge. Furthermore, it has been demonstrated that hot-carrier degradation becomes more pronounced in most recent ultra-scaled MOSFETs. Finally, the situation is made even more complicated due to HCD acceleration by self-heating typical for these 3D transistors .
The faster scaling of the oxide thickness compared to the operating voltage leads to an increase of the oxide fields during normal device operation, resulting in an increased tunneling current. In this context, direct tunneling (DT) which is independent of the electric field for low oxide fields and Fowler-Nordheim tunneling where only a reduced energy barrier has to be passed have to be addressed, see Figure 4.11. In both tunneling mechanisms an electron is able to tunnel directly through the oxide. Note that for Fowler-Nordheim tunneling a reduced tunnel barrier has to be overcome, a consequence of a high gate voltage.
Another tunneling mechanism is called trap assisted tunneling (TAT) wherein two or more defects located in the oxide are involved. Such defects are either preexisting or can be created when high electric fields are applied at the gate. The creation of the defects gives rise to stress induced leackage current (SILC), where an increased gate leakage current is measured at low electric fields [59, 60]. This mechanism is particularly important in electrically erasable programmable read-only-memoriess (EEPROMs) where the gate dielectric is repeatedly subjected to high electric fields during writing and erasing cycles. An increase of the gate leakage current at low gate bias conditions triggers self-discharging of memory cells and is therefore mainly responsible for the degradation of the data retention time . As SILC increases with decreasing oxide thickness, it has been identified as one of the main showstopper for further scaling of non-volatile memories [45, 62].
As mentioned previously, charge capture and emission in oxide traps becomes visible as discrete steps in the drain-source current when a device is sufficiently small. Quite remarkably, in such nanoscale transistors discrete charge capture and emission events are also visible in the gate current provided that the oxide is thin enough [63, 64], see Figure 4.12.
A decrease in the gate current is sometimes correlated with an increase of the drain current, while sometimes the opposite behavior is seen. The anti-correlation between discrete transitions which can be seen in the gate and drain current is typically observed in SiON pMOSFETs, where a high-level of the drain current can correspond to a low-level of the gate leakage current and vice versa , see Figure 4.12. To result in a low-level leakage current, the oxide trap has to be neutral. In this state, the defect does not perturb the surface potential along the conducting channel and hence does not degrade the drain current, leading to the observed high-level of the drain-source current. In contrast, a discrete increase of the gate current causes a discrete step in the drain current towards a smaller value. This observation is related to a hole capture event of the single trap, which then becomes positively charged. Furthermore, the charged trap perturbs the surface potential along the channel and causes the drain current to decrease. When single trap SILC is studied in SiON nMOSFETs, correlated low and high current levels of the gate leakage current and drain current are typically observed . Conversely, in high-k metal gate nMOSFETs anti-correlated charge capture and emission events are visible in the drain-source and gate current . This contradiction requires closer inspection to fully understand the origins of charge trapping causing the correlated and anti-correlated fluctuations of the drain-source and gate current.
Nonetheless, the repeated charging and discharging of the defect and the correlated changes in the gate current give arise to single defect SILC which is visible in nanoscale devices only. Analogously to classical BTI investigations, in large area devices the vast number of defects and their ultra-small step heights do not allow to identify them individually.
To explain SILC and BTI separately, several models have been proposed recently [65, 66, MWC17, 67]. However, by studying single defect SILC, it has been demonstrated that the same defects are responsible for BTI and SILC . Therefore, to reliably describe the interplay between SILC and BTI, a unified description of charge trapping is required. This can be achieved by using the four-state NMP, which is discussed on Section 7.3.3. As discussed later, this model appears promising to explain SILC and BTI. However, to settle this claim, further investigations are required.« PreviousUpNext »Contents