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12.3 NBTI in Large Area SiGe Transistors
Next, the recovery behavior of large-area SiGe pMOSFETs, W=1 µm and L=1 µm, subjected to NBTI stress is studied. In contrast to their nanoscale counterparts, where single defects can be studied, the average recovery of a large
number of defects is recorded for these devices. The reason is that for an increasing device area 
a smaller average contribution of a single charge 
is obtained (the indices nm and um denote the nanoscale and large-area devices, respectively).
To monitor the recovery of the large-area transistors, a conventional extended measure-stress-measure (eMSM) scheme is used [184]. Each eMSM cycle is recorded at the same stress and recovery bias conditions and at the same device temperature. For a measurement cycle the stress and recovery times are varied as given below.
![\[ \begin {pmatrix} \tStress \\ \tRead \end {pmatrix} = \begin {pmatrix} \SI {1}{\milli \second } & \SI {10}{\milli \second } & \ldots & \SI {10}{\second } & \SI {100}{\second } & \SI {1}{\kilo \second } \\
\SI {100}{\second } & \SI {100}{\second } & \ldots & \SI {100}{\second } & \SI {1}{\kilo \second } & \SI {10}{\kilo \second } \\ \end {pmatrix} \]](diss-images/image-1210.svg)
Furthermore, the gate bias during stress is varied in the range of ![\( \VGStress \in \left [\SI {-1.6}{\volt },\SI {-1.7}{\volt },...,\SI {-2.4}{\volt } \right ] \)](diss-images/02C3F01ED359799B2BA67E565041515E.svg)
, the gate voltage during recovery is set to 
and the device temperature is not changed during a complete eMSM sequence. For each measurement cycle a fresh device has been used.
As can be seen from the recovery traces shown in Figure 12.13 (symbols), the sensitivities of the DUTs to NBTI stress for all three different technologies follow the same trend as observed for the nanoscale devices, see Figure 12.7 (right).
Figure 12.13: The recorded recovery on large-area devices subjected to NBTI stress with increasing stress times and two different stress biases for the devices with (top) 
and (bottom) the reference Si pMOSFET. The recovery characteristics for all cases can be well described by our simulations and the four-state NMP model. Furthermore, a considerably stronger stress bias dependence of the threshold voltage shift is
visible for the devices with a SiGe quantum well which is also explained by our simulations [MWJ2].
Again, the devices with 
show the smallest threshold voltage shift whereas the devices with 
as well as the reference devices degrade much more.
To reproduce the recovery behavior of the large-area devices the four-state NMP model is used together with a large defect distribution. The four-state NMP model nicely explains the 
recovery recorded at different stress times and biases, visible in Figure 12.7 (right) for the devices with 
and the reference transistor. Quite remarkably, the recovery of all three pMOSFETs is captured using the same set of defect parameters for the four-state NMP model. From the good fit we conclude that the trap parameters are a property of the gate
stack rather that a property of the different channel layout. As a consequence, the device lifetime is solely determined by the band offsets in the channel/Si cap layer.
Previous: 12.2 Single Charge Trapping Top: 12 Negative Bias Temperature Instabilities in High-k SiGe Transistors Next: 12.4 Nanoscale versus Large-Area Devices