« PreviousUpNext »Contents
Previous: 4.7 Measurement Methods and Motivation    Next: 5.2 Impact on Devices

Part I Theory

5 Bias Temperature Instabilities

Bias temperature instabilities (BTI) are one of the most prominent degradation mechanism in modern semiconductor devices and are a serious threat to the performance of n-channel an p-channel MOSFETs. The detrimental impact of BTI on the device behavior can be observed when a large bias is applied at the gate contact of the device. This bias is typically referred to as the stress bias. Furthermore, the device temperature plays an important role in context of BTI. Thus elevated temperatures are used during investigations concerning BTI.

An almost inexhaustible amount of literature is available on this puzzling phenomenon, wherein the controversial origins of the detrimental impact on the device performance are discussed. This chapter provides an overview of BTI, starting with a qualitative description of BTI in various technologies, followed by an introduction of the impact of BTI on the device behavior. Afterwards the consequences of device degradation on circuits are presented, and finally the time-dependent variability is introduced.

5.1 Phenomenological Classification

In general, BTI is classified into positive BTI (PBTI) and negative BTI (NBTI), where the terms positive and negative refer to the sign of the gate bias. Most commonly NBTI is typically studied in pMOSFETs while PBTI has received more attention in nMOSFETs while NBTI/nMOSFETs and PBTI/pMOSFETs investigations are rather rare because their impact on the device performance is less pronounced. Furthermore, carrying out NBTI/nMOSFETs and PBTI/pMOSFETs experiments is rather difficult, because most test structures contain ESD protection diodes. These diodes are implemented to protect the gate oxide from any unwanted electrostatic discharges. A disadvantage of such ESD diodes is the suppression of large positive/negative gate voltages on pMOSFETs/nMOSFETs thereby making NBTI/nMOSFETs and PBTI/pMOSFETs investigations difficult. However, for the development of a detailed picture of charge trapping, i.e. defect energy levels and distributions inside gate dielectrics, ideally both NBTI and PBTI have to be carefully analyzed on nMOSFETs and pMOSFETs at the same time.

To illustrate the importance of BTI in modern CMOS applications a simple inverter circuit is shown in Figure 5.1.

(-tikz- diagram)

Figure 5.1:  A simple CMOS inverter can be made by connecting one nMOSFET and one nMOSFET in series sharing the gate contact. The input and output voltages are shown as well as the corresponding gate biases. During \( \Vinp =\VDD \) the nMOSFET is subjected to PBTI stress whereas the phases with \( \Vinp =\SI {0}{\volt } \) are responsible for NBTI stress of the pMOSFET.

The inverter uses one pMOSFET and one nMOSFET which are connected in series. At any time one MOSFETs is subjected to BTI stress as both devices are controlled by a common gate terminal. While the input voltage of the inverter is a logical one, i.e. \( \VG =\VDD \), the nMOSFET is subjected to positive bias stress. In contrast, a logical zero signal applied at the input, i.e. \( \VG =\SI {0}{\volt } \), results in \( \VGS =-\VDD \) at the pMOSFET and is equivalent to negative bias stress of this transistor. As a consequence, NBTI and PBTI are both important phenomena in CMOS applications.

« PreviousUpNext »Contents
Previous: 4.7 Measurement Methods and Motivation    Next: 5.2 Impact on Devices