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14  MOSFET Characterization Array

To study the immunity of a particular device technology to BTI or HCD only a handful of devices from the same wafer is typically studied. With the measurement data and simulations from these investigations in hand the susceptibility of these technology to BTI and HCD is afterwards predicted. The devices used in these studies are thereby least often directly aligned next to each other on the wafer. As a consequence, the device variability which is unavoidably introduced during the device fabrication process can cause slight variations of the experimental data. Such variations are particularly important in nanoscale devices where different RDD distributions can lead to significant device-to-device variations, which are in case of RDD mainly notable by variations of the device threshold voltage. Nonetheless, in order to understand a particular technology, a detailed characterization of a large number of single defects measurable only at nanoscale devices is necessary. Therefore a statistically relevant number of devices have to be probed. In order to suppress the device-to-device variations for such a rigorous reliability study as good as possible transistor arrays can be employed. The big advantage of transistor arrays is that due to the densely packed transistors die-to-die and across wafer variations between seemingly identical devices can be excluded. For this purpose special test structures containing numerous transistors organized as an array, can be used. Figure 14.1 compares the number of devices for different structures using the same chip area.


Figure 14.1:  The micro-photography shows the number of transistors for (top) an array structure, (middle) single devices, and (bottom) a pipelined array [189] available at chip areas of the same dimensions, after [190].

As can be seen, a large number of transistors can be accessed when transistors are organized as arrays [191].

In the following, the concept of the recently fabricated test structure is presented. The array, solely controlled by the TMI, is used to collect measurement data from numerous single defects. Finally, measurement results of the first investigations are presented.

14.1 Array Structure

To evaluate charge trapping in high-k metal gate (HKMG) MOSFETs, the test array was fabricated in a commercial \( \SI {28}{\nano \meter } \) HKMG technology. All fabricated devices are connected to a common source and a common bulk contact, see Figure 14.2.


Figure 14.2:  The schematic of the array structure shows nMOSFETs and pMOSFETs arranged in a large device matrix. All devices share a common source and common bulk connection whereas the drain and gate connections are controlled by electrical switches. To assure accurate voltage levels at the drain and gate contact, Kelvin pads (sense and force) are used, after [190].

In contrast, the electrical path between the external gate and drain pins and the corresponding terminals of the selected DUT are controlled by an additional integrated circuit. It is important to note that the drain and gate connections to the devices are separated into \( \VD   \) and \( \VG    \) pins for the transistor which is currently measured and into the analog signals \( \VDoff   \), \( \VGPoff   \), and \( \VGNoff    \) connecting all the appropriate terminals of the corresponding transistors remaining in their “off” state. To study the impact of the gate area on the average step height of a charge capture and emission event, the number of active traps and the trapping kinetics of transistors with different geometries are available, summarized in Table 14.1.

W | L \( \SI {30}{\nano \meter } \) \( \SI {90}{\nano \meter } \) \( 3\times \SI {30}{\nano \meter } \) \( \SI {150}{\nano \meter } \)
\( \SI {100}{\nano \meter } \) * * * *
\( \SI {200}{\nano \meter } \) *
\( \SI {300}{\nano \meter } \) *

Table 14.1:  The device geometries of the transistors available in the array structure. For each gate area 4536 single pMOSFETs and nMOSFETs are available. A long gate device is emulated by serially stacked transistors (\( 3\times \SI {30}{\nano \meter } \) structure), after [190].

For instance, it has been reported that the average step height of a single trap and the number of active traps scale with the device area as \( \eta _\mathrm {s}=\eta /A \) and \( N_\mathrm {T,s}=\NT \times A \), respectively. Using the designed test structure, these relations can be verified for the high-k technology.

The overall test structure, including circuitry electronic for device selection as well as all external lines, is shown in Figure 14.3.

(-tikz- diagram)

Figure 14.3:  The test chip and the control components, digital control lines and transistors is shown. Both transistors types, namely pMOSFETs and nMOSFETs, with different geometries are available within this test structure. The drain and gate terminal of the selected DUT are separated from the corresponding terminals remaining transistors while common source and bulk connections are used. For device selection four control lines are available, after [190].

To allow Kelvin sensing, the gate and drain signals have transmission gates placed on each side of the structure. Additionally, the device selection uses shift registers controlled by three digital signals, “clock”, “data” and “enable”, for the gate and drain connection.

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