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4.2  Variability and Yield

During the device fabrication process variations between seemingly identical devices are unavoidable. As such process variations cause a deviation of the device behavior from its ideal characteristics they can have a detrimental impact on the performance of single devices and circuits [8]. In this context, the yield, defined as [9]

(4.2) \begin{equation} \text {Yield} = \frac {\text {number of devices which work properly}}{\text {number of fabricated devices}} \end{equation}

is also seriously affected by these variations [9]. Inherently, the yield can be further considered in terms of failure-types, classified into [10]

  • (i) catastrophic yield losses, hypernym for all chips which do not work due to functional failures, and

  • (ii) parametric yield losses, covering all devices which are properly operating, but however, do not meet certain power or performance criteria.

The process variations, referred to as time-zero device variability, are considered contributors to parametric yield losses, are distributed across the wafer and are unavoidably introduced because of a limited controlability of the fabrication process [11]. They can be classified into [12]

  • (i) local and random variations within a die or within a single structure with only a few transistors,

  • (ii) variations across a single wafer due to inhomogeneities during processing, and

  • (iii) variations between different wafers in a lot due to changing processing conditions during the manufacturing process.

Fluctuations in the surface roughness and thickness of patterned structures contribute to line edge roughness (LER) and are the cause of a stochastic variation of the device geometry [13]. The metal grain roughness (MGR) has to be considered in high-k transistors, as these devices require a metal gate contact on top of the high-k dielectrics. Because the work-function of the metal layer depends on the orientation of metal grains random variations of the threshold voltage are introduced [14]. Random discrete dopands (RDDs) play a very important role in scaled transistors as the random placement of the small number of dopand atoms available in such devices causes fluctuations of the threshold voltage of more than tens of millivolt [15, 16, 17, 18]. The impact of the random discrete dopand (RDD) fluctuations on the standard deviation of the threshold voltage \( \sigmaVth \) can be approximately expressed by an analytic function [19]

(4.3) \begin{equation} \sigmaVth ^2 \approx \sqrt [2]{4q^3\epsSi \phiB } \left (\frac {\tox }{\epsox }\right )^2 \frac {\sqrt [2]{\Ntot }}{\WtimesL } \end{equation}

with (math image) the surface potential and (math image) the doping concentration. Most important, \( \sigmaVth \) depends on oxide thickness (math image) and the total dopand concentration (math image). Further examples for process variations are annealing effects and lithographic limitations [19, 11, 20].

In general, the variation of the physical parameters constraints systematic and random contributions. Assuming these to be statistically independent, the total variance is obtained as [21, 22, 23, 24]

(4.4) \begin{equation} \sigma ^2_\mathrm {var} = \sigma ^2_\mathrm {rand} + \sigma ^2_\mathrm {syst} \end{equation}

with the variances of the and random and systematic components \( \sigma ^2_\mathrm {rand} \) and \( \sigma ^2_\mathrm {syst} \), respectively. However, to account for the constituents properly they have to be isolated and characterized independently of each other, which can be very difficult [11].

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