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12 Negative Bias Temperature Instabilities in High-k SiGe Transistors

To sustain Moores' Law, conventional MOSFETs have been scaled down to the nanometer regime. However, due to the limited subthreshold slope, the device supply voltages cannot be scaled in the same manner as the device geometry without any losses of the device performance. As a consequence, the oxide fields occurring in the scaled devices increase, thereby leading to an increase of the gate leakage current. In order to avoid the detrimental increase of the gate leakage currents, high-k (HK) gate stacks together with metal gate (MG) contacts are used in state-of-the-art MOSFETs. The fabricated high-k gate stack employed in such devices typically consists of a Hafniumoxide (\( \HfO    \)) layer on top of a (math image) interfacial layer [2, 3, 4, 5]. Just like with transistors using (math image) or (math image) gate dielectrics, BTI is one of the most critical reliability issues in HK transistors as well.

To further enhance the performance of transistors, SiGe quantum-well pMOSFETs have been proposed [175, 176, 177, 178], see Figure 12.1 (left).

(-tikz- diagram)


Figure 12.1:  (left) Schematic view of the studied high-k metal gate (HKMG) devices show a thin Si cap layer on top of a strained (math image) layer. In this work, nanoscale and large-area devices with two different Si cap layer thicknesses of (math image) and (math image) and a reference Si transistor have been studied in detail. Therefore quantum-mechanical simulations and classical devices simulations have been carried out. While the quantum-mechanical simulations have been performed using a simplified 1D model given by a cut perpendicular to the channel through the middle of gate contact, the latter uses 2D devices structures. (right) The (math image) characteristics of all studied large-area and nanoscale devices show that the threshold voltage and the sub-threshold slope (SS) vary with the thickness of the Si cap layer. The threshold voltage is extracted as the gate voltage at which \( \IDS =\SI {-70}{\nano \ampere }\cdot W/L \). As can be seen, the devices with the thin Si cap layer have the largest threshold voltage \( \Vth   \) whereas the reference devices show the smallest \( \Vth   \) [MWJ2, MWJ1].

These transistors employ HK gate stacks on top of a SiGe quantum-well layer, and have been initially developed to take advantage of the higher carrier mobility of the strained SiGe layer. Quite surprisingly, it was found that NBTI is considerably smaller in these quantum-well devices. Furthermore, a strong dependence of the absolute threshold voltage shift on the Si cap layer thickness together with a stronger oxide field acceleration with respect to Si devices was reported. It has been speculated that these observations are a consequence of the energetical realignment of the SiGe channel with respect to the gate stack [175, MWC24]. As the previous observations were made on large-area devices, a more precise justification was difficult to give. As previously mentioned, using large-area devices only the average response of a large number of defects can be studied. However, to provide a more detailed understanding of this phenomenon, the impact of the individual constituents has to be studied.

To study the impact of the Si cap layer thickness on the device performance devices with two different geometries are compared, namely nanoscale SiGe pMOSFETs with a gate width of \( W=\SI {90}{\nano \meter } \) and a gate length of \( L=\SI {35}{\nano \meter } \), and large-area SiGe pMOSFETs with \( W=L=\SI {1}{\micro \meter } \). For each geometry three different device variants, namely devices with a Si cap layer thickness of (math image) and (math image), as well as a conventional Si transistor which is the reference device, are studied. The (math image) characteristics of the corresponding devices is shown in Figure 12.1 (left). A strong correlation between the threshold voltage, extracted as the voltage at which \( \IDS =\SI {-70}{\nano \ampere }\cdot W/L \), and the Si cap layer thickness is visible. The devices with the thin Si cap layer show the highest threshold voltage whereas the lowest values are observed for the reference devices. These different threshold voltages have to be considered during NBTI characterization when stress and recovery experiments are performed. In general, the oxide stress field (math image) can be estimated by

(12.1) \begin{equation} \EOxStrEff \approx \frac {\VGateOv }{\dEOT }=\frac {\VGStress -\Vth }{\dEOT } \label {equ:Eoverdrive} \end{equation}

with (math image) the gate overdrive voltage, (math image) the effective oxide thickness, (math image) the stress voltage and (math image) the threshold voltage of the device. In order to apply similar stress and recovery oxide fields different gate voltages have to be used for the stress/measure experiments carried out at the different device variants. This is particularly important as the degradation and recovery of the threshold voltage strongly depends on the stress and recovery oxide field.

In the following section, the impact of NBTI on nanoscale and large-area SiGe HKMG pMOSFETs is investigated. Starting with the description of the device electrostatics using quantum-mechanical and classical device simulations, the device structure and doping profiles are reproduced. Next, the TDDS is used to study single defects in nanoscale pMOSFETs. By employing the four-state NMP model, see Section 7.3.3, the charge transition times of single defects are explained. Afterwards, charge trapping in large-area SiGe devices is discussed and modeled using the four-state NMP model in combination with our classical device simulator Minimos-NT. Finally, the lifetime projections which are based on our simulations are presented.

12.1 Device Simulation

At the begin of our investigations the device structure has to be created. Therefore quantum-mechanical (QM) and classical device simulations are carried out. The QM simulations are necessary to consider quantum-effects in nanoscale devices and are performed on a simplified 1D device structure. Afterwards, classical devices simulations are performed using Minimos-NT and a 2D device structure. The latter simulations are required to apply our four-state NMP model to explain charge trapping in these devices.

12.1.1 Quantum Mechanical Simulations

As the thin SiGe channel underneath the Si cap layer requires careful consideration, detailed QM simulations are carried out. These are performed by using our QM Schrödinger Poisson solver VSP to calibrate the device structures to the experimental \( \CV    \) characteristics of large-area devices with \( W=L=\SI {10}{\micro \meter } \) [179, 180]. This is achieved by thoroughly adjusting the individual layer thicknesses using a simplified one-dimensional structure of our transistor, see Figure 12.1. From the QM simulations the band structure and the corresponding sub-bands are obtained and shown in Figure 12.2.


Figure 12.2:  The band diagrams of (top) the reference device and (bottom) the device with (math image) are shown at stress bias conditions. The wavefunctions (WF) of the corresponding subbands highlighted are calculated with our Schrödinger-Poisson solver. Note that for the SiGe device the peaks of the wavefunctions are located in the SiGe and near the SiGe/Si cap interface. Consequently, the current is dominantly located inside the SiGe layer. In contrast, for the reference device the peaks of the wavefunctions, and as a consequence the conducting channel, are closer to the (math image)/Si interface. This observation is very important, because the closer the traps are located to the channel the larger the step heights are, compare CCDF presented in part one [MWJ1]. As the device variants have different threshold voltages, the band diagrams are calculated at the same overdrive voltage in order to obtain comparable carrier concentrations in the inversion layer.The band-diagram of the device with (math image) at stress bias conditions [MWJ2].

The peaks of the first two wavefunctions in the subbands are located in the (math image) near the (math image)/(math image) interface. As the subbands give the probability of finding the carriers, the peaks in the (math image) suggest that the conducting channel is more likely located in the SiGe layer than in the Si cap layer. Furthermore, the charge separately calculated for the SiGe and Si cap layer at different gate biases for the different device variants is notably larger inside the SiGe layer than in the Si cap layer, see Figure 12.3.

(-tikz- diagram)

Figure 12.3:  The hole concentration for the Si cap layer and the SiGe layer is calculated at different gate biases from our QM simulations. As can be seen, the charge present in the SiGe layer exceeds the charge of the Si cap layer, confirming the channel to be more likely located in the SiGe layer. The inset gives the ratio between the charge in the SiGe and Si cap layers. With increasing Si cap layer thickness, the channel in the SiGe is less pronounced, a behavior that weakens the superior NBTI behavior of the SiGe devices [MWJ2].

This result confirms the previous claim that the channel is primarily in the SiGe layer and is particularly important when charge trapping is considered in these devices. The prevalent channel inside the (math image) layer will be demonstrated to be the cause for the reduced susceptibility of the (math image) device to NBTI.

12.1.2 Classical Device Simulations

Based on the layer thicknesses and bulk doping density obtained from the one-dimensional QM simulations, the two-dimensional device structures of the pMOSFETs are created. For this purpose, the classical device simulator Minimos-NT [181] is used and a quantum-corrected drift-diffusion model is solved [182].

As can be seen from Figure 12.4, the simulations which have been performed using the calibrated 2D devices nicely reproduce the experimental (math image) characteristics.


Figure 12.4:  The (math image) characteristics of the large-area (open symbols) and the nanoscale pMOSFETs (closed symbols) have been measured using the TMI. Using the classical device simulator Minimos-NT the characteristics can be nicely reproduced. This has been achieved using the same device structure with the corresponding Si cap layer thicknesses and an appropriate gate area [MWJ2].

From our 2D device simulation the surface potential and the carrier concentration at the interface can be calculated. Both quantities are used in combination with the four-state NMP model to explain the intricate capture and emission times of the single defects measured on our nanoscale devices and the continuous recovery observed on large-area transistors. Note that all (math image) characteristics have been reproduced using the same devices structure with an appropriate gate area and the corresponding Si cap layer thickness.

Based on our classical device simulations the band-diagram of our SiGe devices can be calculated. In Figure 12.5 the valance and conduction band edges are shown at stress bias conditions.


Figure 12.5:  The band-diagram of the SiGe transistor with (math image) is shown with the corresponding active energy region (AER) calculated for a stress bias of \( \VGStress =\SI {-2.4}{\volt } \) and a recovery bias of \( \VGRead =\SI {-0.2}{\volt } \). As can be seen, the AERs are separated into an area which can exchange their charge with the MG (red) and in an AER (blue) for charge exchange with the conducting channel. Additionally, the conducting channel at the SiCap/(math image) interface is shown in the AER (dotted line) [MWJ2].

In addition, the so called active energy region (AER) for charge trapping is highlighted in the band-diagram. This area is very important as it is a necessary condition for a single defect contributing to NBTI that at defined stress and recovery bias conditions the defect is energetically located inside such an AER. Only those defects which are energetically arranged inside the AER can change their charge state during stress and thus contribute to a change in the threshold voltage. The borders of the AER are defined by the considered stress and recovery gate bias. Thus at stress bias conditions the energetic level (math image) of a defect located at (math image) inside the gate stack has to lie above the corresponding Fermi level (math image)

(12.2) \begin{equation} \ET + q\VGStress -q\phiStr (\xT ) > \EF \label {equ:condStress} \end{equation}

and below the Fermi-level at recovery bias conditions

(12.3) \begin{equation} \ET + q\VGRead -q\phiRead (\xT ) < \EF \label {equ:condRead} \end{equation}

with \( \phiStr (x) \) and \( \phiRead (x) \) the position dependent potential drop across the gate stack for stress and recovery bias conditions, respectively. Furthermore, the AER region can be separated into an AER for charge trapping with the MG and into an AER for charge trapping with the conduction channel. Both AERs can be described using (12.2) and (12.3) with its corresponding Fermi levels. Additionally, the energy level of the conducting channel located in the SiGe, which is by itself determined by the (math image) dependent band offset between the Si cap and SiGe, is visible in the AER in Figure 12.5. As this certain energy level is higher than the Fermi level of the Si cap only a reduced number of defects can capture a hole from the SiGe.

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