At the begin of this thesis a brief introduction into the recent advances of the semiconductor industry is given, starting with the fast progress in device scaling. Afterwards, a short summary of the main reliability issues which have to be addressed in modern transistors is presented. To study the degradation of the device performance, sophisticated measurement methods are required. A short overview of proposed experimental methods is thus discussed next. Due to considerable limitations of conventional available measurement setups, we finally developed our own custom-made measurement instrument. Detailed information on the motivation for our own investigations is finally provided.
Complementary metal-oxide-semiconductor (CMOS) technology, which combines n- and p-type metal-oxide-semiconductor (MOS) transistors as the basic building blocks for circuits, is the cornerstone of the enormous success of the semiconductor technology which is today present in a vast number of applications, thereby simplifying and enhancing our lives in a variety of ways. During the last decades the challenge for the semiconductor industry was to keep pace with Moore’s Law, which predicts doubling of the density of the transistors approximately every two years  in order to improve performance and reduce production costs. In addition to the scaling of the width and lengths of the transistors, scaling rules require that the insulating layer is also thinned accordingly. Unfortunately, due to the limited subthreshold slope, the supply voltages cannot be scaled in the same manner as the device geometry without deteriorating the ratio between the on and off currents, see Figure 4.1.
Also, the thickness of the insulating layer has to be kept above a certain critical thickness in order to avoid excessive leakage currents. As a consequence, the electric fields inside the devices have increased considerably over the last decades. To overcome this detrimental trend, alternative dielectric materials are required. Therefore, gate stacks using high-k materials together with metal-gate contacts have been introduced and are commonly used in state-of-the-art devices. A typical high-k gate stack consists of a Hafniumoxide () layer on top of an interfacial layer [2, 3, 4, 5]. The equivalent oxide thickness effective oxide thickness (EOT) for such a gate stack is given by the relation
with the layer thicknesses and , and the permitivities and of the and , respectively. High-k gate stacks are nowadays common for planar devices integrated in high-performance complementary metal-oxide-semiconductor (CMOS) applications. To further enhance the performance of CMOS applications the use of high mobility channels is considered [6, 7]. This can be achieved for instance by introducing a SiGe channel which has a higher mobility than the conventionally used silicon, thereby resulting in larger on currents.« PreviousUpNext »Contents