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6 Main Features of Bias Temperature Instabilities

Most commonly BTI is studied in terms of an equivalent threshold voltage shift which occurs when a device is subjected to stress. As the device performance changes particularly slowly at use conditions, the experiments are usually performed at significantly larger biases and temperatures which are called accelerated stress conditions. With the results obtained from voltage and temperature accelerated tests, analytical or empirical models can be derived, calibrated and then used to predict the impact of BTI on the device performance at nominal operating conditions. Therefore, sophisticated models are required which have to provide an accurate description for temperature and field dependent effects.

6.1 Temperature Dependence

To illustrate the temperature dependence of the threshold voltage shift after the transistor has been subjected to NBTI stress, several recovery traces on a large-area pMOSFET are measured after the transistor has been stressed. The measured recovery of the threshold voltage is plotted after normalization to \( \dVth (\text {\@}\tRead =\SI {1}{\micro \second }) \) in Figure 6.1.

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Figure 6.1:  The recovery traces of a large-area device (\( \WtimesL =\SI {10}{\micro \meter }\times \SI {10}{\micro \meter } \)) are shown recorded at four different temperatures after the device has been stressed for (top) \( \tStress =\SI {513.4}{\second } \) and (bottom) \( \tStress =\SI {12.6}{\kilo \second } \). Furthermore the recovery (math image) characteristics is normalized to \( \dVth (\text {\@}\tRead =\SI {1}{\milli \second }) \). As can be seen, a similar recovery behavior is obtained at different temperatures, which reveals that at a first glance the device recovery only shows a weak or negligible temperature dependence.

Most notably, a similar recovery behavior is obtained for (math image) recovery traces measured at different temperatures. As demonstrated in the following, this observation is important because by studying large-area devices the recovery seems to have only a weak temperature dependence. In contrast, a strong temperature dependence is obtained when the average emission time of single defects is studied in detail on nanoscale devices, see Figure 6.2.

(image)

Figure 6.2:  In nanoscale devices (schematic for pMOSFET with \( \WtimesL =\SI {150}{\nano \meter }\times \SI {100}{\nano \meter } \)) the recovery proceeds in discrete steps. As single defects produce exponentially distributed emission times around their average emission time, the traces for each temperature are calculated by averaging 100 single traces. Clearly visible, at higher temperatures the emission events move towards shorter emission times. The given activation energies (math image) are calculated using an Arrhenious' law.

Using such scaled transistors, the temperature activation of the charge trapping kinetics is directly visible, emphasizing the need for experiments on small devices.

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