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Part III Results

11 Positive Bias Temperature Instabilities in SiON n-channel MOSFETs

The main focus of the research on charge trapping in (math image) transistors was primarily put on NBTI in pMOSFETs. By probing nanoscale pMOSFETs employing the TDDS single defects have been studied with the following properties:

  • i) Nanoscale devices show discrete recovery behavior

  • ii) Single traps show fixed trap and switching trap charge capture and emission time characteristics when the stress and recovery gate bias is varied

  • iii) Temperature dependence of the charge transition times with activation energies in the range of \( \SI {0.5}{\electronvolt } \) up to \( \SI {1.4}{\electronvolt } \) for charge capture and emission were found, mostly limited by the experimental resolution as the time constants depend exponentially an the activation energy

  • iv) Charge capture shows a notable frequency dependence when AC stress biases are applied

  • v) Widely distributed step heights and transition times are visible

  • vi) Defects in pMOSFETs are considered to be hole traps

All these observations have been consistently explained by our four-state NMP model. These findings, however, raise the question whether the defects causing PBTI in nMOSFETs show a similar response to the variation of the bias conditions and temperature or not. To settle this question the TDDS technique has been applied to characterize PBTI in pMOSFETs where electron traps are typically considered to contribute to the threshold voltage shift (math image).

Again, to separate individual emission events belonging to different defects, the devices used for TDDS must only show a handful of defects. However, recent reports have revealed that pMOSFETs show an approximately ten times higher trap density than their nMOSFET counterparts (\( \NPMOS \approx 10\times \NNMOS \)) [93, 172]. As a consequence, just a few carefully selected nanoscale nMOSFETs would show a noticeable number of defects visible in the recovery traces. Thus to efficiently apply the TDDS for PBTI/nMOSFET measurements a device with a scaled gate area of \( \APMOS \approx 10\times \ANMOS \) has been deliberately chosen, compared to our previous studies [123, 142, 173]. As the average step height inversely scales with the gate area, considerably smaller threshold voltage shifts are obtained due to single electron emission events, visible in the recovery traces depicted in Figure 11.1

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Figure 11.1:  Five selected recovery traces with each discrete step corresponding to the emission of a single electron. The traces have been recorded on an nMOSFET (\( W=\SI {0.16}{\micro \meter } \), \( L=\SI {2}{\micro \meter } \)) after BTI stress with \( \tStress = \SI {100}{\second } \) and \( \VGStress = \SI {2.2}{\volt } \). As clearly visible, the step heights of the discrete charge transitions are in the range of \( \dVth \approx \SI {0.15}{\milli \volt } \) and lower, a consequence of the relatively large device area. Such small step heights are equivalent to drain-source current fluctuations below \( \SI {1}{\nano \ampere } \) and increase the experimental effort. As in the NBTI/pMOSFET case, the emission times are distributed over a large time scale [MWC20].

In the following the behavior of electron traps is studied in a nanoscale nMOSFET with \( W=\SI {0.16}{\micro \meter } \) and \( L=\SI {2}{\micro \meter } \) when the transistor is subjected to PBTI stress, for various bias conditions and temperatures. The stress voltages have been varied in the range of \( \SI {1.4}{\volt } \leq \VGStress \leq \SI {2.2}{\volt } \), the stress times between \( \SI {100}{\micro \second } \leq \tStress \leq \SI {100}{\second } \), and the device temperature from \( \SI {50}{\celsius } \) up to \( \SI {80}{\celsius } \). In order to collect a statistically relevant amount of data, the device has been repeatedly stressed and the recovery behavior recorded and analyzed [MWC26], see Figure 11.1.

To check the statistical relevance of the different observed step heights, the CCDF of nMOSFETs and pMOSFETs (\( W=\SI {150}{\nano \meter } \), \( L=\SI {120}{\nano \meter } \)) of the same technology but different geometries are compared in Figure 11.2. To account for the dependence of the step heights on the geometry, the CCDF of the step heights is multiplied by the gate area. Furthermore, the CCDF in Figure 11.2 demonstrates that the step heights in (math image) nMOSFETs also roughly follow an exponential distribution, similar to defects causing NBTI in pMOSFETs. As a consequence, the defects in nMOSFETs and pMOSFETs are expected to have a similar distribution inside the device.

(image)

Figure 11.2:  The CCDF of the step heights multiplied by the gate area \( A = \WtimesL \) is depicted for nMOSFETs and pMOSFETs of the same technology ((math image) oxide with an EOT of \( \dEOT =\SI {2.2}{\nano \meter } \)). The CCDFs of the normalized step heights have a similar shape so that the defects in both devices are expected to have the same spatial depth distribution within the oxide. As a further consequence, traps causing PBTI in nMOSFETs have a similar electrostatic impact on the conducting channel as observed in pMOSFETs when NBTI is studied. The above statistics are extracted from recovery traces with \( \tRead =\SI {1}{\kilo \second } \) of several devices after oxide stress conditions of \( \VGStress =\SI {2.4}{\volt } \) for \( \tStress =\SI {100}{\second } \) [MWC20].

In the investigated pMOSFETs, three defects, namely \( n_1 \) with \( \taue \approx \SI {100}{\milli \second } \) and \( d\approx \SI {0.15}{\milli \volt } \), \( n_4 \) with \( \taue \approx \SI {100}{\milli \second } \) and \( d\approx \SI {0.48}{\milli \volt } \), and \( n_5 \) with \( \taue \approx \SI {1}{\second } \) and \( d\approx \SI {0.26}{\milli \volt } \) could be identified, visible in the spectral map of Figure 11.3 at \( \SI {50}{\celsius } \), at a recovery voltage of \( \VGRead =\SI {0.41}{\volt } \) after stressing the device at \( \VGStress =\SI {2.2}{\volt } \). Both the capture and emission processes have been found to be temperature dependent. This behavior is reflected by the spectral maps in Figure 11.3 (left) and Figure 11.3 (middle) as the single clusters move towards lower emission times for increasing device temperature. Additionally, new defects are shifted into the measurement window at higher temperatures. This is in agreement with previous observations from NBTI/pMOS experiments confirming a strongly thermally activated electron emission similar to that of hole traps [MWC25]. As can be seen from the spectral maps in Figure 11.3 the necessity of a very high measurement resolution is obvious. This is especially the case for defect \( n_1 \) which shows a step height of \( d\approx \SI {0.15}{\milli \volt } \).

(image)

(image)

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Figure 11.3:  The nMOSFET used for this study shows a handful of defects. The individual defects identified by clusters in the above spectral maps move towards lower emission times when the device temperature is increased (\( \SI {50}{\celsius } \) left, \( \SI {65}{\celsius } \) middle). Compared to previous studies on NBTI/pMOSFETs (W=\( \SI {150}{\nano \meter } \), L=\( \SI {120}{\nano \meter } \)) [123] (right), defects observed in PBTI/nMOSFET experiments show a similar response to the device temperature. Note that the single defects show very small step heights due to the investigated device area posing a challenge to the experimental design. From the three defects identified (n\( _1 \), n\( _4 \), n\( _5 \)), defects n\( _1 \) and n\( _4 \) are studied in more detail [MWC20].

In Figure 11.4 the Arrhenius’ plot of the defects n\( _1 \) and n\( _4 \) is shown when the device temperature \( T \) is varied between \( \SI {50}{\celsius } \) and \( \SI {85}{\celsius } \). The thermally induced change of the capture and emission times of the defects n\( _1 \) and n\( _4 \) are approximated by an Arrhenius’ law with activation energies \( \EA \) in the range of \( \SI {0.37}{\electronvolt } \leq \EA \leq \SI {0.9}{\electronvolt } \) for both electron capture and emission. In previous studies activation energies \( \EA \) for pMOSFETs have been found to be within the same range [MWC25]. This indicates, that defects causing PBTI on nMOSFETs follow the same temperature activated mechanism as the defects causing NBTI on pMOSFETs.

(image)

Figure 11.4:  The temperature dependent capture and emission time constants recorded after BTI stress with \( \VGStress =\SI {2.2}{\volt } \) and \( \tStress =\SI {10}{\volt } \) are visualized in an Arrhenius plot. The particular activation energies \( \EA \) assume similar values as those observed for pMOSFETs [123, 173, MWC20].

Two out of the three identified defects, namely \( n_1 \) and \( n_4 \), are studied in detail. The emission time of \( n_1 \) is independent of the applied recovery bias and remains constant over a wide recovery voltage range, see Figure 11.5. Quite to the contrary, the observed emission times of defect \( n_4 \) shows a strong recovery voltage dependence. Towards higher gate voltages the emission times \( \taue \) saturate and become bias-independent, see Figure 11.6.

(-tikz- diagram)

Figure 11.5:  The gate voltage dependence of the capture time \( \tauc \) and the emission time \( \taue \) is shown for defect \( n_1 \). The emission time appears to be independent of the applied bias (fixed charge trap) whereas the capture time shows a significant dependence. Good agreement between data (symbols) and model (lines) is obtained. The inset shows the configuration coordinate diagram of the NMP model required to fit the data [MWC20].

(-tikz- diagram)

Figure 11.6:  Contrary to defect \( n_1 \), the emission time of defect \( n_4 \) shows a very strong dependence on the gate voltage, a behavior attributed to switching traps. Just like the fixed charge trap behavior, the switching trap behavior can be well explained by the four-state NMP model (lines). The inset shows the configuration coordinate diagram of the NMP model [MWC20].

The capture time \( \tauc \) of the defects \( n_1 \) and \( n_4 \) depends exponentially on the stress recovery gate voltage \( \VGRead \) and shows a strong temperature dependence. Both defects show a similar temperature activation for charge capture and emission, see Figure 11.4. Additionally, an evaluation of the model against the experimental TDDS data is given in Figure 11.5 and Figure 11.6. As can be seen, the trapping kinetics can be nicely explained by the four-state NMP model.

As recoverable BTI and RTN are apparently caused by the same defects [127, 174], the bias conditions under which RTN from particular defects can be measured, becomes predictable [MWC25]. Therefore two conditions have to be fulfilled: (i) The carrier capture and emission times \( \tauc \) and \( \taue \) have to be about the same order of magnitude and (ii) the sum of the capture and emission time has to be smaller than the TDDS measurement window \( \tauc +\taue \ll \tRead \) and (iii) the sampling frequency has to be selected that \( \fs << 1/\tauc \) and \( \fs << 1/\taue \). The first condition is necessary in order to ensure that the charge capture and charge emission events occur within a certain time window. Conversely, for \( \tauc <\taue \) the defect will more favorable remain in its charge state and it will take very long for the charge emission to occur. For \( \tauc >\taue \) the defect will be mainly neutral and it will take very to for the defect to become charged. Considering defect \( n_4 \), the first prerequisite is fulfilled near the intersection point of the capture and emission times estimated by the NMP model. The second prerequisite is necessary to ensure that both charge transitions occur withing the TDDS measurement window \( \tauc +\taue \ll \tRead \). To account for the third condition the choice of the sampling frequency and the recovery time plays an important role. The sampling frequency has to be selected that \( \fs << 1/\tauc \) and \( \fs << 1/\taue \) because otherwise the charge transitions are to fast and will not be visible in the measurement traces.

By considering the previously mentioned requirements capture and emission times can be extracted from RTN. As can be seen in Figure 11.6 (yellow circles) several charge transition time data points for defect \( n_4 \) in the gate voltage range of \( \SI {1.0}{\volt } \leq \VG \leq \SI {1.2}{\volt } \) at \( T=\SI {65}{\celsius } \) are extracted from such RTN signal.

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